@@ -141,6 +141,7 @@ void ModuloScheduleExpander::generatePipelinedLoop() {
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MachineInstr *NewMI = cloneInstr (CI, MaxStageCount, StageNum);
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updateInstruction (NewMI, false , MaxStageCount, StageNum, VRMap);
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KernelBB->push_back (NewMI);
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+ LIS.InsertMachineInstrInMaps (*NewMI);
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InstrMap[NewMI] = CI;
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}
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@@ -150,6 +151,7 @@ void ModuloScheduleExpander::generatePipelinedLoop() {
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MachineInstr *NewMI = MF.CloneMachineInstr (&MI);
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updateInstruction (NewMI, false , MaxStageCount, 0 , VRMap);
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KernelBB->push_back (NewMI);
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+ LIS.InsertMachineInstrInMaps (*NewMI);
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InstrMap[NewMI] = &MI;
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}
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@@ -179,6 +181,10 @@ void ModuloScheduleExpander::generatePipelinedLoop() {
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// Add branches between prolog and epilog blocks.
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addBranches (*Preheader, PrologBBs, KernelBB, EpilogBBs, VRMap);
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+ // The intervals of newly created virtual registers are calculated after the
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+ // kernel expansion.
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+ calculateIntervals ();
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+
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delete[] VRMap;
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delete[] VRMapPhi;
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}
@@ -226,6 +232,7 @@ void ModuloScheduleExpander::generateProlog(unsigned LastStage,
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cloneAndChangeInstr (&*BBI, i, (unsigned )StageNum);
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updateInstruction (NewMI, false , i, (unsigned )StageNum, VRMap);
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NewBB->push_back (NewMI);
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+ LIS.InsertMachineInstrInMaps (*NewMI);
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InstrMap[NewMI] = &*BBI;
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}
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}
@@ -303,6 +310,7 @@ void ModuloScheduleExpander::generateEpilog(
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MachineInstr *NewMI = cloneInstr (In, UINT_MAX, 0 );
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updateInstruction (NewMI, i == 1 , EpilogStage, 0 , VRMap);
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NewBB->push_back (NewMI);
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+ LIS.InsertMachineInstrInMaps (*NewMI);
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InstrMap[NewMI] = In;
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}
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}
@@ -343,14 +351,11 @@ void ModuloScheduleExpander::generateEpilog(
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// / basic block with ToReg.
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static void replaceRegUsesAfterLoop (Register FromReg, Register ToReg,
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MachineBasicBlock *MBB,
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- MachineRegisterInfo &MRI,
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- LiveIntervals &LIS) {
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+ MachineRegisterInfo &MRI) {
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for (MachineOperand &O :
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llvm::make_early_inc_range (MRI.use_operands (FromReg)))
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if (O.getParent ()->getParent () != MBB)
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O.setReg (ToReg);
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- if (!LIS.hasInterval (ToReg))
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- LIS.createEmptyInterval (ToReg);
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}
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// / Return true if the register has a use that occurs outside the
@@ -544,8 +549,10 @@ void ModuloScheduleExpander::generateExistingPhis(
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if (VRMap[LastStageNum - np - 1 ].count (LoopVal))
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PhiOp2 = VRMap[LastStageNum - np - 1 ][LoopVal];
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- if (IsLast && np == NumPhis - 1 )
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- replaceRegUsesAfterLoop (Def, NewReg, BB, MRI, LIS);
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+ if (IsLast && np == NumPhis - 1 ) {
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+ replaceRegUsesAfterLoop (Def, NewReg, BB, MRI);
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+ NoIntervalRegs.push_back (NewReg);
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+ }
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continue ;
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}
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}
@@ -563,6 +570,7 @@ void ModuloScheduleExpander::generateExistingPhis(
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TII->get (TargetOpcode::PHI), NewReg);
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NewPhi.addReg (PhiOp1).addMBB (BB1);
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NewPhi.addReg (PhiOp2).addMBB (BB2);
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+ LIS.InsertMachineInstrInMaps (*NewPhi);
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if (np == 0 )
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InstrMap[NewPhi] = &*BBI;
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@@ -584,8 +592,10 @@ void ModuloScheduleExpander::generateExistingPhis(
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// Check if we need to rename any uses that occurs after the loop. The
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// register to replace depends on whether the Phi is scheduled in the
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// epilog.
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- if (IsLast && np == NumPhis - 1 )
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- replaceRegUsesAfterLoop (Def, NewReg, BB, MRI, LIS);
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+ if (IsLast && np == NumPhis - 1 ) {
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+ replaceRegUsesAfterLoop (Def, NewReg, BB, MRI);
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+ NoIntervalRegs.push_back (NewReg);
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+ }
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// In the kernel, a dependent Phi uses the value from this Phi.
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if (InKernel)
@@ -603,9 +613,12 @@ void ModuloScheduleExpander::generateExistingPhis(
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// Check if we need to rename a Phi that has been eliminated due to
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// scheduling.
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if (NumStages == 0 && IsLast) {
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- auto It = VRMap[CurStageNum].find (LoopVal);
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- if (It != VRMap[CurStageNum].end ())
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- replaceRegUsesAfterLoop (Def, It->second , BB, MRI, LIS);
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+ auto &CurStageMap = VRMap[CurStageNum];
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+ auto It = CurStageMap.find (LoopVal);
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+ if (It != CurStageMap.end ()) {
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+ replaceRegUsesAfterLoop (Def, It->second , BB, MRI);
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+ NoIntervalRegs.push_back (It->second );
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+ }
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}
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}
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}
@@ -705,6 +718,7 @@ void ModuloScheduleExpander::generatePhis(
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TII->get (TargetOpcode::PHI), NewReg);
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NewPhi.addReg (PhiOp1).addMBB (BB1);
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NewPhi.addReg (PhiOp2).addMBB (BB2);
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+ LIS.InsertMachineInstrInMaps (*NewPhi);
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if (np == 0 )
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InstrMap[NewPhi] = &*BBI;
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@@ -724,8 +738,10 @@ void ModuloScheduleExpander::generatePhis(
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rewriteScheduledInstr (NewBB, InstrMap, CurStageNum, np, &*BBI, Def,
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NewReg);
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}
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- if (IsLast && np == NumPhis - 1 )
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- replaceRegUsesAfterLoop (Def, NewReg, BB, MRI, LIS);
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+ if (IsLast && np == NumPhis - 1 ) {
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+ replaceRegUsesAfterLoop (Def, NewReg, BB, MRI);
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+ NoIntervalRegs.push_back (NewReg);
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+ }
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}
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}
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}
@@ -834,9 +850,11 @@ void ModuloScheduleExpander::splitLifetimes(MachineBasicBlock *KernelBB,
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// We split the lifetime when we find the first use.
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if (!SplitReg) {
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SplitReg = MRI.createVirtualRegister (MRI.getRegClass (Def));
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- BuildMI (*KernelBB, MI, MI->getDebugLoc (),
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- TII->get (TargetOpcode::COPY), SplitReg)
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- .addReg (Def);
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+ MachineInstr *newCopy =
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+ BuildMI (*KernelBB, MI, MI->getDebugLoc (),
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+ TII->get (TargetOpcode::COPY), SplitReg)
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+ .addReg (Def);
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+ LIS.InsertMachineInstrInMaps (*newCopy);
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}
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BBJ.substituteRegister (Def, SplitReg, 0 , *TRI);
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}
@@ -904,13 +922,17 @@ void ModuloScheduleExpander::addBranches(MachineBasicBlock &PreheaderBB,
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removePhis (Epilog, LastEpi);
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// Remove the blocks that are no longer referenced.
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if (LastPro != LastEpi) {
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+ for (auto &MI : *LastEpi)
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+ LIS.RemoveMachineInstrFromMaps (MI);
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LastEpi->clear ();
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LastEpi->eraseFromParent ();
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}
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if (LastPro == KernelBB) {
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LoopInfo->disposed (&LIS);
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NewKernel = nullptr ;
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}
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+ for (auto &MI : *LastPro)
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+ LIS.RemoveMachineInstrFromMaps (MI);
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LastPro->clear ();
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LastPro->eraseFromParent ();
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} else {
@@ -931,6 +953,14 @@ void ModuloScheduleExpander::addBranches(MachineBasicBlock &PreheaderBB,
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}
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}
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+ // / Some registers are generated during the kernel expansion. We calculate the
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+ // / live intervals of these registers after the expansion.
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+ void ModuloScheduleExpander::calculateIntervals () {
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+ for (Register Reg : NoIntervalRegs)
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+ LIS.createAndComputeVirtRegInterval (Reg);
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+ NoIntervalRegs.clear ();
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+ }
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+
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// / Return true if we can compute the amount the instruction changes
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// / during each iteration. Set Delta to the amount of the change.
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bool ModuloScheduleExpander::computeDelta (MachineInstr &MI, unsigned &Delta) {
@@ -1051,8 +1081,10 @@ void ModuloScheduleExpander::updateInstruction(MachineInstr *NewMI,
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Register NewReg = MRI.createVirtualRegister (RC);
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MO.setReg (NewReg);
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VRMap[CurStageNum][reg] = NewReg;
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- if (LastDef)
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- replaceRegUsesAfterLoop (reg, NewReg, BB, MRI, LIS);
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+ if (LastDef) {
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+ replaceRegUsesAfterLoop (reg, NewReg, BB, MRI);
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+ NoIntervalRegs.push_back (NewReg);
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+ }
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} else if (MO.isUse ()) {
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MachineInstr *Def = MRI.getVRegDef (reg);
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// Compute the stage that contains the last definition for instruction.
@@ -1201,10 +1233,11 @@ void ModuloScheduleExpander::rewriteScheduledInstr(
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UseOp.setReg (ReplaceReg);
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else {
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Register SplitReg = MRI.createVirtualRegister (MRI.getRegClass (OldReg));
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- BuildMI (*BB, UseMI, UseMI->getDebugLoc (), TII-> get (TargetOpcode::COPY ),
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- SplitReg)
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- .addReg (ReplaceReg);
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+ MachineInstr *newCopy = BuildMI (*BB, UseMI, UseMI->getDebugLoc (),
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+ TII-> get (TargetOpcode::COPY), SplitReg)
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+ .addReg (ReplaceReg);
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UseOp.setReg (SplitReg);
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+ LIS.InsertMachineInstrInMaps (*newCopy);
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}
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}
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}
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