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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt -p loop-vectorize -S %s | FileCheck %s |
| 3 | + |
| 4 | +target triple = "arm64-apple-macosx11.0.0" |
| 5 | + |
| 6 | +define void @fshl_operand_first_order_recurrence(ptr %dst, ptr noalias %src) { |
| 7 | +; CHECK-LABEL: define void @fshl_operand_first_order_recurrence( |
| 8 | +; CHECK-SAME: ptr [[DST:%.*]], ptr noalias [[SRC:%.*]]) { |
| 9 | +; CHECK-NEXT: [[ENTRY:.*]]: |
| 10 | +; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] |
| 11 | +; CHECK: [[VECTOR_PH]]: |
| 12 | +; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| 13 | +; CHECK: [[VECTOR_BODY]]: |
| 14 | +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| 15 | +; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <2 x i64> [ <i64 poison, i64 0>, %[[VECTOR_PH]] ], [ [[WIDE_LOAD1:%.*]], %[[VECTOR_BODY]] ] |
| 16 | +; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 |
| 17 | +; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 2 |
| 18 | +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP0]] |
| 19 | +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP1]] |
| 20 | +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 0 |
| 21 | +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 2 |
| 22 | +; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i64>, ptr [[TMP4]], align 8 |
| 23 | +; CHECK-NEXT: [[WIDE_LOAD1]] = load <2 x i64>, ptr [[TMP5]], align 8 |
| 24 | +; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[VECTOR_RECUR]], <2 x i64> [[WIDE_LOAD]], <2 x i32> <i32 1, i32 2> |
| 25 | +; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i64> [[WIDE_LOAD]], <2 x i64> [[WIDE_LOAD1]], <2 x i32> <i32 1, i32 2> |
| 26 | +; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> <i64 1, i64 1>, <2 x i64> [[TMP6]], <2 x i64> <i64 1, i64 1>) |
| 27 | +; CHECK-NEXT: [[TMP9:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> <i64 1, i64 1>, <2 x i64> [[TMP7]], <2 x i64> <i64 1, i64 1>) |
| 28 | +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP0]] |
| 29 | +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[TMP1]] |
| 30 | +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[TMP10]], i32 0 |
| 31 | +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[TMP10]], i32 2 |
| 32 | +; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr [[TMP12]], align 8 |
| 33 | +; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr [[TMP13]], align 8 |
| 34 | +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| 35 | +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 |
| 36 | +; CHECK-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| 37 | +; CHECK: [[MIDDLE_BLOCK]]: |
| 38 | +; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <2 x i64> [[WIDE_LOAD1]], i32 1 |
| 39 | +; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]] |
| 40 | +; CHECK: [[SCALAR_PH]]: |
| 41 | +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 100, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| 42 | +; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] |
| 43 | +; CHECK-NEXT: br label %[[LOOP:.*]] |
| 44 | +; CHECK: [[LOOP]]: |
| 45 | +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] |
| 46 | +; CHECK-NEXT: [[RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[L:%.*]], %[[LOOP]] ] |
| 47 | +; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]] |
| 48 | +; CHECK-NEXT: [[L]] = load i64, ptr [[GEP_SRC]], align 8 |
| 49 | +; CHECK-NEXT: [[OR:%.*]] = tail call i64 @llvm.fshl.i64(i64 1, i64 [[RECUR]], i64 1) |
| 50 | +; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]] |
| 51 | +; CHECK-NEXT: store i64 [[OR]], ptr [[GEP_DST]], align 8 |
| 52 | +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| 53 | +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], 100 |
| 54 | +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] |
| 55 | +; CHECK: [[EXIT]]: |
| 56 | +; CHECK-NEXT: ret void |
| 57 | +; |
| 58 | +entry: |
| 59 | + br label %loop |
| 60 | + |
| 61 | +loop: |
| 62 | + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| 63 | + %recur = phi i64 [ 0, %entry ], [ %l, %loop ] |
| 64 | + %gep.src = getelementptr inbounds i64, ptr %src, i64 %iv |
| 65 | + %l = load i64, ptr %gep.src, align 8 |
| 66 | + %or = tail call i64 @llvm.fshl.i64(i64 1, i64 %recur, i64 1) |
| 67 | + %gep.dst = getelementptr inbounds i64, ptr %dst, i64 %iv |
| 68 | + store i64 %or, ptr %gep.dst, align 8 |
| 69 | + %iv.next = add i64 %iv, 1 |
| 70 | + %exitcond.not = icmp eq i64 %iv, 100 |
| 71 | + br i1 %exitcond.not, label %exit, label %loop |
| 72 | + |
| 73 | +exit: |
| 74 | + ret void |
| 75 | +} |
| 76 | + |
| 77 | +declare i64 @llvm.fshl.i64(i64, i64, i64) |
| 78 | +;. |
| 79 | +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} |
| 80 | +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} |
| 81 | +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} |
| 82 | +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} |
| 83 | +;. |
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