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[RISCV][TableGen] Generate RISCVTargetParserDef.inc from the new RISCVExtension tblgen information. (#89335)
Instead of using RISCVISAInfo's extension information, use the extension found in tblgen after #89326. We still need to use RISCVISAInfo code to get the sorting rules for the ISA string. The ISA string we generate now is not quite the same extension we had before. No implied extensions are included in the generate string unless they are explicitly listed in RISCVProcessors.td. This primarily affects Zicsr being implied by F, V implying Zve*, and Zvl*b implying a smaller Zvl*b. All of these implication should be picked up when the string is used by the frontend. The benefit is that we get a more manageable ISA string for humans to deal with. This is a step towards generating RISCVISAInfo's extension list from tblgen.
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‎llvm/test/TableGen/riscv-target-def.td

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// RUN: llvm-tblgen -gen-riscv-target-def -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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class RISCVExtension<string name, int major, int minor, string fieldname,
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string desc, list<SubtargetFeature> implies = [],
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string value = "true">
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: SubtargetFeature<name, fieldname, value, desc, implies> {
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int MajorVersion = major;
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int MinorVersion = minor;
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bit Experimental = false;
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}
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def FeatureStdExtI
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: RISCVExtension<"i", 2, 1, "HasStdExtI",
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"'I' (Base Integer Instruction Set)">;
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def FeatureStdExtZicsr
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: RISCVExtension<"zicsr", 2, 0, "HasStdExtZicsr",
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"'zicsr' (CSRs)">;
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def FeatureStdExtZifencei
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: RISCVExtension<"zifencei", 2, 0, "HasStdExtZifencei",
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"'Zifencei' (fence.i)">;
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def Feature32Bit
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: SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
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def Feature64Bit
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: SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
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// Dummy feature that isn't an extension.
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def FeatureDummy
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: SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
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class RISCVProcessorModel<string n,
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SchedMachineModel m,
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list<SubtargetFeature> f,
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list<SubtargetFeature> tunef = [],
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string default_march = "">
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: ProcessorModel<n, m, f, tunef> {
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string DefaultMarch = default_march;
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}
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class RISCVTuneProcessorModel<string n,
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SchedMachineModel m,
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list<SubtargetFeature> tunef = [],
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list<SubtargetFeature> f = []>
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: ProcessorModel<n, m, f,tunef>;
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def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
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NoSchedModel,
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[Feature32Bit,
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FeatureStdExtI]>;
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def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI]>;
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def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>;
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def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
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NoSchedModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureDummy]>;
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def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureDummy]>;
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def ROCKET : RISCVTuneProcessorModel<"rocket",
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NoSchedModel>;
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// CHECK: #ifndef PROC
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// CHECK: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)
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// CHECK: #endif
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// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0)
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// CHECK: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0)
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// CHECK: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zifencei2p0"}, 0)
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// CHECK: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zifencei2p0"}, 0)
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// CHECK: #undef PROC
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// CHECK: #ifndef TUNE_PROC
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// CHECK: #define TUNE_PROC(ENUM, NAME)
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// CHECK: #endif
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// CHECK: TUNE_PROC(GENERIC, "generic")
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// CHECK: TUNE_PROC(ROCKET, "rocket")
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// CHECK: #undef TUNE_PROC

‎llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

Lines changed: 32 additions & 23 deletions
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using namespace llvm;
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using ISAInfoTy = llvm::Expected<std::unique_ptr<RISCVISAInfo>>;
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// We can generate march string from target features as what has been described
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// in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
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// Naming Conventions'.
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//
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// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
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// get feature name from feature records instead of feature bits.
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static std::string getMArch(const Record &Rec) {
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std::vector<std::string> FeatureVector;
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unsigned XLen = 32;
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static void printMArch(raw_ostream &OS, const Record &Rec) {
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std::map<std::string, RISCVISAInfo::ExtensionVersion,
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RISCVISAInfo::ExtensionComparator>
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Extensions;
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unsigned XLen = 0;
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// Convert features to FeatureVector.
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for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
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StringRef FeatureName = Feature->getValueAsString("Name");
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if (llvm::RISCVISAInfo::isSupportedExtensionFeature(FeatureName))
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FeatureVector.push_back((Twine("+") + FeatureName).str());
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else if (FeatureName == "64bit")
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if (Feature->isSubClassOf("RISCVExtension")) {
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unsigned Major = Feature->getValueAsInt("MajorVersion");
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unsigned Minor = Feature->getValueAsInt("MinorVersion");
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Extensions[FeatureName.str()] = {Major, Minor};
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} else if (FeatureName == "64bit") {
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assert(XLen == 0 && "Already determined XLen");
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XLen = 64;
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} else if (FeatureName == "32bit") {
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assert(XLen == 0 && "Already determined XLen");
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XLen = 32;
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}
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}
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ISAInfoTy ISAInfo = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
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if (!ISAInfo)
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report_fatal_error("Invalid features");
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assert(XLen != 0 && "Unable to determine XLen");
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OS << "rv" << XLen;
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// RISCVISAInfo::toString will generate a march string with all the extensions
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// we have added to it.
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return (*ISAInfo)->toString();
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ListSeparator LS("_");
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for (auto const &Ext : Extensions)
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OS << LS << Ext.first << Ext.second.Major << 'p' << Ext.second.Minor;
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}
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static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
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// Iterate on all definition records.
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for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
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std::string MArch = Rec->getValueAsString("DefaultMarch").str();
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// Compute MArch from features if we don't specify it.
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if (MArch.empty())
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MArch = getMArch(*Rec);
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bool FastScalarUnalignedAccess =
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any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
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return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
@@ -73,9 +74,17 @@ static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
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bool FastUnalignedAccess =
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FastScalarUnalignedAccess && FastVectorUnalignedAccess;
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OS << "PROC(" << Rec->getName() << ", "
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<< "{\"" << Rec->getValueAsString("Name") << "\"}, "
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<< "{\"" << MArch << "\"}, " << FastUnalignedAccess << ")\n";
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OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
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<< "\"}, {\"";
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StringRef MArch = Rec->getValueAsString("DefaultMarch");
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// Compute MArch from features if we don't specify it.
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if (MArch.empty())
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printMArch(OS, *Rec);
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else
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OS << MArch;
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OS << "\"}, " << FastUnalignedAccess << ")\n";
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}
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OS << "\n#undef PROC\n";
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OS << "\n";

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