[SelectionDAG] Use logic right shift to avoid loop hang

Issue was reported in D149033, `Val` can be negative value and
arithmetic right shift always keeps the sign bit.

BTW, the redundant code `Val = -Val` is removed by this patch.

Author: KanRobert

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -5459,9 +5459,6 @@ static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
 
     if (DAG.getTargetLoweringInfo().isBeneficialToExpandPowI(
             Val, DAG.shouldOptForSize())) {
-      // Get the exponent as a positive value.
-      if (Val < 0)
-        Val = -Val;
       // We use the simple binary decomposition method to generate the multiply
       // sequence.  There are more optimal ways to do this (for example,
       // powi(x,15) generates one more multiply than it should), but this has
@@ -5481,7 +5478,8 @@ static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
 
         CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
                                 CurSquare, CurSquare);
-        Val >>= 1;
+        // Use logic right shift
+        Val = int(unsigned(Val) >> 1);
       }
 
       // If the original was negative, invert the result, producing 1/(x*x*x).

llvm/test/CodeGen/X86/powi-negative-imm.ll

@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
+
+define void @test_powi(ptr %p) nounwind {
+; CHECK-LABEL: powi:
+; CHECK:             pushq %rax
+; CHECK-NEXT:        movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-COUNT-31:    mulss %xmm1, %xmm1
+; CHECK-NEXT:        movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:        divss %xmm1, %xmm0
+; CHECK-NEXT:        callq foo@PLT
+; CHECK-NEXT:        popq %rax
+; CHECK-NEXT:        retq
+bb:
+  %load = load float, ptr %p, align 4
+  %call1 = call contract float @llvm.powi.f32.i32(float %load, i32 -2147483648)
+  %call2 = call i1 @foo(float %call1)
+  ret void
+}
+
+declare zeroext i1 @foo(float)
+declare float @llvm.powi.f32.i32(float, i32)