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[MIRPrinter] Don't print space when there is no successor (#80143)
Extra space causes the checks generated by update_mir_test_checks to be unavailable. ``` # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 # RUN: llc -mtriple=x86_64-- -o - %s -run-pass=none -verify-machineinstrs -simplify-mir | FileCheck %s --- name: foo body: | ; CHECK-LABEL: name: foo ; CHECK: bb.0: ; CHECK-NEXT: successors: ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.1: ; CHECK-NEXT: RET 0, $eax bb.0: successors: bb.1: RET 0, $eax ... ``` The failure log is as follows: ``` llvm/test/CodeGen/MIR/X86/unreachable-block-print.mir:9:16: error: CHECK-NEXT: is on the same line as previous match ; CHECK-NEXT: {{ $}} ^ <stdin>:21:13: note: 'next' match was here successors: ^ <stdin>:21:13: note: previous match ended here successors: ```
1 parent 9bf4e54 commit b7738e2

10 files changed

+117
-110
lines changed

‎llvm/lib/CodeGen/MIRPrinter.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -694,7 +694,9 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
694694
// fallthrough.
695695
if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
696696
!canPredictSuccessors(MBB)) {
697-
OS.indent(2) << "successors: ";
697+
OS.indent(2) << "successors:";
698+
if (!MBB.succ_empty())
699+
OS << " ";
698700
for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
699701
if (I != MBB.succ_begin())
700702
OS << ", ";

‎llvm/test/CodeGen/AArch64/GlobalISel/uaddo-8-16-bits.mir

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ body: |
2424
; CHECK-NEXT: G_BR %bb.1
2525
; CHECK-NEXT: {{ $}}
2626
; CHECK-NEXT: bb.1:
27-
; CHECK-NEXT: successors:{{ $}}
27+
; CHECK-NEXT: successors:
2828
; CHECK-NEXT: {{ $}}
2929
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
3030
; CHECK-NEXT: {{ $}}
@@ -78,7 +78,7 @@ body: |
7878
; CHECK-NEXT: G_BR %bb.1
7979
; CHECK-NEXT: {{ $}}
8080
; CHECK-NEXT: bb.1:
81-
; CHECK-NEXT: successors:{{ $}}
81+
; CHECK-NEXT: successors:
8282
; CHECK-NEXT: {{ $}}
8383
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
8484
; CHECK-NEXT: {{ $}}
@@ -132,7 +132,7 @@ body: |
132132
; CHECK-NEXT: G_BR %bb.1
133133
; CHECK-NEXT: {{ $}}
134134
; CHECK-NEXT: bb.1:
135-
; CHECK-NEXT: successors:{{ $}}
135+
; CHECK-NEXT: successors:
136136
; CHECK-NEXT: {{ $}}
137137
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
138138
; CHECK-NEXT: {{ $}}
@@ -204,7 +204,7 @@ body: |
204204
; CHECK-NEXT: G_BR %bb.1
205205
; CHECK-NEXT: {{ $}}
206206
; CHECK-NEXT: bb.1:
207-
; CHECK-NEXT: successors:{{ $}}
207+
; CHECK-NEXT: successors:
208208
; CHECK-NEXT: {{ $}}
209209
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
210210
; CHECK-NEXT: {{ $}}
@@ -259,7 +259,7 @@ body: |
259259
; CHECK-NEXT: G_BR %bb.1
260260
; CHECK-NEXT: {{ $}}
261261
; CHECK-NEXT: bb.1:
262-
; CHECK-NEXT: successors:{{ $}}
262+
; CHECK-NEXT: successors:
263263
; CHECK-NEXT: {{ $}}
264264
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
265265
; CHECK-NEXT: {{ $}}
@@ -315,7 +315,7 @@ body: |
315315
; CHECK-NEXT: G_BR %bb.1
316316
; CHECK-NEXT: {{ $}}
317317
; CHECK-NEXT: bb.1:
318-
; CHECK-NEXT: successors:{{ $}}
318+
; CHECK-NEXT: successors:
319319
; CHECK-NEXT: {{ $}}
320320
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
321321
; CHECK-NEXT: {{ $}}
@@ -375,7 +375,7 @@ body: |
375375
; CHECK-NEXT: G_BR %bb.1
376376
; CHECK-NEXT: {{ $}}
377377
; CHECK-NEXT: bb.1:
378-
; CHECK-NEXT: successors:{{ $}}
378+
; CHECK-NEXT: successors:
379379
; CHECK-NEXT: {{ $}}
380380
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
381381
; CHECK-NEXT: {{ $}}
@@ -510,7 +510,7 @@ body: |
510510
; CHECK-NEXT: G_BR %bb.3
511511
; CHECK-NEXT: {{ $}}
512512
; CHECK-NEXT: bb.2:
513-
; CHECK-NEXT: successors:{{ $}}
513+
; CHECK-NEXT: successors:
514514
; CHECK-NEXT: {{ $}}
515515
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
516516
; CHECK-NEXT: {{ $}}
@@ -575,7 +575,7 @@ body: |
575575
; CHECK-NEXT: G_BR %bb.1
576576
; CHECK-NEXT: {{ $}}
577577
; CHECK-NEXT: bb.1:
578-
; CHECK-NEXT: successors:{{ $}}
578+
; CHECK-NEXT: successors:
579579
; CHECK-NEXT: {{ $}}
580580
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
581581
; CHECK-NEXT: {{ $}}
@@ -632,7 +632,7 @@ body: |
632632
; CHECK-NEXT: G_BR %bb.1
633633
; CHECK-NEXT: {{ $}}
634634
; CHECK-NEXT: bb.1:
635-
; CHECK-NEXT: successors:{{ $}}
635+
; CHECK-NEXT: successors:
636636
; CHECK-NEXT: {{ $}}
637637
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
638638
; CHECK-NEXT: {{ $}}
@@ -690,7 +690,7 @@ body: |
690690
; CHECK-NEXT: G_BR %bb.1
691691
; CHECK-NEXT: {{ $}}
692692
; CHECK-NEXT: bb.1:
693-
; CHECK-NEXT: successors:{{ $}}
693+
; CHECK-NEXT: successors:
694694
; CHECK-NEXT: {{ $}}
695695
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
696696
; CHECK-NEXT: {{ $}}
@@ -781,7 +781,7 @@ body: |
781781
; CHECK-NEXT: G_BR %bb.1
782782
; CHECK-NEXT: {{ $}}
783783
; CHECK-NEXT: bb.1:
784-
; CHECK-NEXT: successors:{{ $}}
784+
; CHECK-NEXT: successors:
785785
; CHECK-NEXT: {{ $}}
786786
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
787787
; CHECK-NEXT: {{ $}}

‎llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -416,15 +416,15 @@ body: |
416416
; CHECK-NEXT: B %bb.14
417417
; CHECK-NEXT: {{ $}}
418418
; CHECK-NEXT: bb.14.bb86:
419-
; CHECK-NEXT: successors:{{ $}}
419+
; CHECK-NEXT: successors:
420420
; CHECK-NEXT: {{ $}}
421421
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
422422
; CHECK-NEXT: $w0 = MOVi32imm 10
423423
; CHECK-NEXT: STATEPOINT 2882400000, 0, 1, @blam, $w0, 2, 0, 2, 0, 2, 41, 2, 0, 2, 1, 2, 0, 2, 237, 2, 3, 2, 14, 2, 0, 2, 0, 2, 0, 2, 3, 2, 4278124286, 2, 3, 2, 4278124286, 2, 0, 2, 0, 2, 7, 2, 0, 2, 7, 2, 4278124286, 2, 7, 2, 4278124286, 2, 7, 2, 4278124286, 2, 7, 2, 4278124286, 2, 7, 2, 0, 2, 7, 2, 4278124286, 2, 7, 2, 0, 2, 7, 2, 4278124286, 2, 7, 2, 0, 2, 7, 2, 4278124286, 2, 0, 2, 0, 2, 7, 2, 0, 2, 1, 2, 0, 2, 0, 2, 1, 0, 0, csr_aarch64_aapcs, implicit-def $sp, implicit-def dead early-clobber $lr
424424
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
425425
; CHECK-NEXT: {{ $}}
426426
; CHECK-NEXT: bb.15.bb90:
427-
; CHECK-NEXT: successors:{{ $}}
427+
; CHECK-NEXT: successors:
428428
; CHECK-NEXT: liveins: $fp, $w21, $x10
429429
; CHECK-NEXT: {{ $}}
430430
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
@@ -434,7 +434,7 @@ body: |
434434
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
435435
; CHECK-NEXT: {{ $}}
436436
; CHECK-NEXT: bb.16.bb94:
437-
; CHECK-NEXT: successors:{{ $}}
437+
; CHECK-NEXT: successors:
438438
; CHECK-NEXT: {{ $}}
439439
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
440440
; CHECK-NEXT: $w0 = MOVi32imm 10

‎llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -84,10 +84,8 @@
8484

8585
declare i8 addrspace(1)* @bar(i8 addrspace(1)*)
8686

87-
; Function Attrs: nounwind readnone
8887
declare i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(token, i32 immarg, i32 immarg) #0
8988

90-
; Function Attrs: nounwind readnone
9189
declare i8 addrspace(1)* @llvm.experimental.gc.result.p1i8(token) #0
9290

9391
declare void @wombat(i32)
@@ -199,7 +197,7 @@ body: |
199197
; CHECK-NEXT: B %bb.2
200198
; CHECK-NEXT: {{ $}}
201199
; CHECK-NEXT: bb.2.bb1:
202-
; CHECK-NEXT: successors:{{ $}}
200+
; CHECK-NEXT: successors:
203201
; CHECK-NEXT: {{ $}}
204202
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
205203
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10
@@ -208,7 +206,7 @@ body: |
208206
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
209207
; CHECK-NEXT: {{ $}}
210208
; CHECK-NEXT: bb.3.bb2:
211-
; CHECK-NEXT: successors:{{ $}}
209+
; CHECK-NEXT: successors:
212210
; CHECK-NEXT: {{ $}}
213211
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
214212
; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 10
@@ -289,7 +287,7 @@ body: |
289287
; CHECK-NEXT: B %bb.14
290288
; CHECK-NEXT: {{ $}}
291289
; CHECK-NEXT: bb.10.bb31:
292-
; CHECK-NEXT: successors:{{ $}}
290+
; CHECK-NEXT: successors:
293291
; CHECK-NEXT: {{ $}}
294292
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
295293
; CHECK-NEXT: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 10
@@ -298,11 +296,11 @@ body: |
298296
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
299297
; CHECK-NEXT: {{ $}}
300298
; CHECK-NEXT: bb.11.bb35:
301-
; CHECK-NEXT: successors:{{ $}}
299+
; CHECK-NEXT: successors:
302300
; CHECK-NEXT: {{ $}}
303301
; CHECK-NEXT: {{ $}}
304302
; CHECK-NEXT: bb.13.bb40:
305-
; CHECK-NEXT: successors:{{ $}}
303+
; CHECK-NEXT: successors:
306304
; CHECK-NEXT: {{ $}}
307305
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
308306
; CHECK-NEXT: [[MOVi32imm3:%[0-9]+]]:gpr32 = MOVi32imm 10
@@ -327,7 +325,7 @@ body: |
327325
; CHECK-NEXT: B %bb.16
328326
; CHECK-NEXT: {{ $}}
329327
; CHECK-NEXT: bb.16.bb47:
330-
; CHECK-NEXT: successors:{{ $}}
328+
; CHECK-NEXT: successors:
331329
; CHECK-NEXT: {{ $}}
332330
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
333331
; CHECK-NEXT: [[MOVi32imm4:%[0-9]+]]:gpr32 = MOVi32imm 14
@@ -336,7 +334,7 @@ body: |
336334
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
337335
; CHECK-NEXT: {{ $}}
338336
; CHECK-NEXT: bb.17.bb49:
339-
; CHECK-NEXT: successors:{{ $}}
337+
; CHECK-NEXT: successors:
340338
; CHECK-NEXT: {{ $}}
341339
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
342340
; CHECK-NEXT: [[MOVi32imm5:%[0-9]+]]:gpr32 = MOVi32imm 10

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ body: |
1515
; GCN-NEXT: S_CBRANCH_EXECNZ %bb.2, implicit $exec
1616
; GCN-NEXT: {{ $}}
1717
; GCN-NEXT: bb.1:
18-
; GCN-NEXT: successors: {{$}}
18+
; GCN-NEXT: successors:
1919
; GCN-NEXT: {{ $}}
2020
; GCN-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1)
2121
; GCN-NEXT: {{ $}}
@@ -47,7 +47,7 @@ body: |
4747
; GCN-NEXT: [[C1:%[0-9]+]]:_(p1) = G_CONSTANT i64 0
4848
; GCN-NEXT: {{ $}}
4949
; GCN-NEXT: bb.1:
50-
; GCN-NEXT: successors: {{$}}
50+
; GCN-NEXT: successors:
5151
; GCN-NEXT: {{ $}}
5252
; GCN-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1)
5353
; GCN-NEXT: {{ $}}

‎llvm/test/CodeGen/ARM/constant-island-movwt.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -893,7 +893,7 @@ body: |
893893
# CHECK-NEXT: t2B %bb.2, 14 /* CC::al */, $noreg
894894
# CHECK-NEXT: {{^ $}}
895895
# CHECK-NEXT: bb.1 (align 4):
896-
# CHECK-NEXT: successors:{{ }}
896+
# CHECK-NEXT: successors:
897897
# CHECK-NEXT: {{^ $}}
898898
# CHECK-NEXT: CONSTPOOL_ENTRY 1, %const.0, 4
899899
# CHECK-NEXT: {{^ $}}

‎llvm/test/CodeGen/MIR/X86/unreachable-block-print.mir

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2+
# RUN: llc -mtriple=x86_64-- -o - %s -run-pass=none -verify-machineinstrs -simplify-mir | FileCheck %s
3+
---
4+
name: foo
5+
body: |
6+
; CHECK-LABEL: name: foo
7+
; CHECK: bb.0:
8+
; CHECK-NEXT: successors:
9+
; CHECK-NEXT: {{ $}}
10+
; CHECK-NEXT: {{ $}}
11+
; CHECK-NEXT: bb.1:
12+
; CHECK-NEXT: RET 0, $eax
13+
bb.0:
14+
successors:
15+
16+
bb.1:
17+
RET 0, $eax
18+
...

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