@@ -38,62 +38,55 @@ define i32 @test1(ptr nocapture %a, i64 %n) {
38
38
; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or disjoint i64 [[INDVARS_IV]], 1
39
39
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]]
40
40
; CHECK: for.exiting_block.1:
41
- ; CHECK-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[TMP0]], 42
42
- ; CHECK-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
41
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
43
42
; CHECK: latch.1:
44
43
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
45
44
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
46
45
; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]]
47
46
; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = or disjoint i64 [[INDVARS_IV]], 2
48
47
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]]
49
48
; CHECK: for.exiting_block.2:
50
- ; CHECK-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[TMP0]], 42
51
- ; CHECK-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
49
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
52
50
; CHECK: latch.2:
53
51
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]]
54
52
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
55
53
; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]]
56
54
; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = or disjoint i64 [[INDVARS_IV]], 3
57
55
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]]
58
56
; CHECK: for.exiting_block.3:
59
- ; CHECK-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[TMP0]], 42
60
- ; CHECK-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
57
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
61
58
; CHECK: latch.3:
62
59
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]]
63
60
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
64
61
; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]]
65
62
; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = or disjoint i64 [[INDVARS_IV]], 4
66
63
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]]
67
64
; CHECK: for.exiting_block.4:
68
- ; CHECK-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[TMP0]], 42
69
- ; CHECK-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
65
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
70
66
; CHECK: latch.4:
71
67
; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]]
72
68
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
73
69
; CHECK-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]]
74
70
; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = or disjoint i64 [[INDVARS_IV]], 5
75
71
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]]
76
72
; CHECK: for.exiting_block.5:
77
- ; CHECK-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[TMP0]], 42
78
- ; CHECK-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
73
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
79
74
; CHECK: latch.5:
80
75
; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]]
81
76
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
82
77
; CHECK-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]]
83
78
; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = or disjoint i64 [[INDVARS_IV]], 6
84
79
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]]
85
80
; CHECK: for.exiting_block.6:
86
- ; CHECK-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[TMP0]], 42
87
- ; CHECK-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
81
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
88
82
; CHECK: latch.6:
89
83
; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]]
90
84
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
91
85
; CHECK-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]]
92
86
; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = or disjoint i64 [[INDVARS_IV]], 7
93
87
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]]
94
88
; CHECK: for.exiting_block.7:
95
- ; CHECK-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[TMP0]], 42
96
- ; CHECK-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
89
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
97
90
; CHECK: latch.7:
98
91
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
99
92
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
@@ -134,12 +127,11 @@ define i32 @test1(ptr nocapture %a, i64 %n) {
134
127
; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[SUM_0_LCSSA_PH]], [[LATCHEXIT_UNR_LCSSA]] ], [ [[ADD_EPIL]], [[LATCHEXIT_EPILOG_LCSSA]] ]
135
128
; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]]
136
129
; CHECK: otherexit.loopexit:
137
- ; CHECK-NEXT: [[SUM_02_LCSSA_PH:%.*]] = phi i32 [ [[SUM_02]], [[FOR_EXITING_BLOCK]] ], [ [[ADD]], [[FOR_EXITING_BLOCK_1]] ], [ [[ADD_1]], [[FOR_EXITING_BLOCK_2]] ], [ [[ADD_2]], [[FOR_EXITING_BLOCK_3]] ], [ [[ADD_3]], [[FOR_EXITING_BLOCK_4]] ], [ [[ADD_4]], [[FOR_EXITING_BLOCK_5]] ], [ [[ADD_5]], [[FOR_EXITING_BLOCK_6]] ], [ [[ADD_6]], [[FOR_EXITING_BLOCK_7]] ]
138
130
; CHECK-NEXT: br label [[OTHEREXIT:%.*]]
139
131
; CHECK: otherexit.loopexit3:
140
132
; CHECK-NEXT: br label [[OTHEREXIT]]
141
133
; CHECK: otherexit:
142
- ; CHECK-NEXT: [[SUM_02_LCSSA:%.*]] = phi i32 [ [[SUM_02_LCSSA_PH ]], [[OTHEREXIT_LOOPEXIT]] ], [ [[SUM_02_EPIL]], [[OTHEREXIT_LOOPEXIT3]] ]
134
+ ; CHECK-NEXT: [[SUM_02_LCSSA:%.*]] = phi i32 [ [[SUM_02 ]], [[OTHEREXIT_LOOPEXIT]] ], [ [[SUM_02_EPIL]], [[OTHEREXIT_LOOPEXIT3]] ]
143
135
; CHECK-NEXT: [[RVAL:%.*]] = call i32 (...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 [[SUM_02_LCSSA]]) ]
144
136
; CHECK-NEXT: ret i32 [[RVAL]]
145
137
;
@@ -774,62 +766,55 @@ define i32 @test5(ptr nocapture %a, i64 %n) {
774
766
; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or disjoint i64 [[INDVARS_IV]], 1
775
767
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_1:%.*]]
776
768
; CHECK: for.exiting_block.1:
777
- ; CHECK-NEXT: [[CMP_1:%.*]] = icmp eq i64 [[TMP0]], 42
778
- ; CHECK-NEXT: br i1 [[CMP_1]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
769
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_1:%.*]]
779
770
; CHECK: latch.1:
780
771
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT]]
781
772
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX_1]], align 4
782
773
; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[TMP4]], [[ADD]]
783
774
; CHECK-NEXT: [[INDVARS_IV_NEXT_1:%.*]] = or disjoint i64 [[INDVARS_IV]], 2
784
775
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_2:%.*]]
785
776
; CHECK: for.exiting_block.2:
786
- ; CHECK-NEXT: [[CMP_2:%.*]] = icmp eq i64 [[TMP0]], 42
787
- ; CHECK-NEXT: br i1 [[CMP_2]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
777
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_2:%.*]]
788
778
; CHECK: latch.2:
789
779
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_1]]
790
780
; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX_2]], align 4
791
781
; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[TMP5]], [[ADD_1]]
792
782
; CHECK-NEXT: [[INDVARS_IV_NEXT_2:%.*]] = or disjoint i64 [[INDVARS_IV]], 3
793
783
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_3:%.*]]
794
784
; CHECK: for.exiting_block.3:
795
- ; CHECK-NEXT: [[CMP_3:%.*]] = icmp eq i64 [[TMP0]], 42
796
- ; CHECK-NEXT: br i1 [[CMP_3]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
785
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_3:%.*]]
797
786
; CHECK: latch.3:
798
787
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_2]]
799
788
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX_3]], align 4
800
789
; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[TMP6]], [[ADD_2]]
801
790
; CHECK-NEXT: [[INDVARS_IV_NEXT_3:%.*]] = or disjoint i64 [[INDVARS_IV]], 4
802
791
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_4:%.*]]
803
792
; CHECK: for.exiting_block.4:
804
- ; CHECK-NEXT: [[CMP_4:%.*]] = icmp eq i64 [[TMP0]], 42
805
- ; CHECK-NEXT: br i1 [[CMP_4]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
793
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_4:%.*]]
806
794
; CHECK: latch.4:
807
795
; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_3]]
808
796
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX_4]], align 4
809
797
; CHECK-NEXT: [[ADD_4:%.*]] = add nsw i32 [[TMP7]], [[ADD_3]]
810
798
; CHECK-NEXT: [[INDVARS_IV_NEXT_4:%.*]] = or disjoint i64 [[INDVARS_IV]], 5
811
799
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_5:%.*]]
812
800
; CHECK: for.exiting_block.5:
813
- ; CHECK-NEXT: [[CMP_5:%.*]] = icmp eq i64 [[TMP0]], 42
814
- ; CHECK-NEXT: br i1 [[CMP_5]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
801
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_5:%.*]]
815
802
; CHECK: latch.5:
816
803
; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_4]]
817
804
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX_5]], align 4
818
805
; CHECK-NEXT: [[ADD_5:%.*]] = add nsw i32 [[TMP8]], [[ADD_4]]
819
806
; CHECK-NEXT: [[INDVARS_IV_NEXT_5:%.*]] = or disjoint i64 [[INDVARS_IV]], 6
820
807
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_6:%.*]]
821
808
; CHECK: for.exiting_block.6:
822
- ; CHECK-NEXT: [[CMP_6:%.*]] = icmp eq i64 [[TMP0]], 42
823
- ; CHECK-NEXT: br i1 [[CMP_6]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
809
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_6:%.*]]
824
810
; CHECK: latch.6:
825
811
; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_5]]
826
812
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX_6]], align 4
827
813
; CHECK-NEXT: [[ADD_6:%.*]] = add nsw i32 [[TMP9]], [[ADD_5]]
828
814
; CHECK-NEXT: [[INDVARS_IV_NEXT_6:%.*]] = or disjoint i64 [[INDVARS_IV]], 7
829
815
; CHECK-NEXT: br label [[FOR_EXITING_BLOCK_7:%.*]]
830
816
; CHECK: for.exiting_block.7:
831
- ; CHECK-NEXT: [[CMP_7:%.*]] = icmp eq i64 [[TMP0]], 42
832
- ; CHECK-NEXT: br i1 [[CMP_7]], label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
817
+ ; CHECK-NEXT: br i1 false, label [[OTHEREXIT_LOOPEXIT]], label [[LATCH_7]]
833
818
; CHECK: latch.7:
834
819
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDVARS_IV_NEXT_6]]
835
820
; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX_7]], align 4
@@ -870,12 +855,11 @@ define i32 @test5(ptr nocapture %a, i64 %n) {
870
855
; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ [[SUM_0_LCSSA_PH]], [[LATCHEXIT_UNR_LCSSA]] ], [ [[ADD_EPIL]], [[LATCHEXIT_EPILOG_LCSSA]] ]
871
856
; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]]
872
857
; CHECK: otherexit.loopexit:
873
- ; CHECK-NEXT: [[RVAL_PH:%.*]] = phi i32 [ [[SUM_02]], [[FOR_EXITING_BLOCK]] ], [ [[ADD]], [[FOR_EXITING_BLOCK_1]] ], [ [[ADD_1]], [[FOR_EXITING_BLOCK_2]] ], [ [[ADD_2]], [[FOR_EXITING_BLOCK_3]] ], [ [[ADD_3]], [[FOR_EXITING_BLOCK_4]] ], [ [[ADD_4]], [[FOR_EXITING_BLOCK_5]] ], [ [[ADD_5]], [[FOR_EXITING_BLOCK_6]] ], [ [[ADD_6]], [[FOR_EXITING_BLOCK_7]] ]
874
858
; CHECK-NEXT: br label [[OTHEREXIT:%.*]]
875
859
; CHECK: otherexit.loopexit3:
876
860
; CHECK-NEXT: br label [[OTHEREXIT]]
877
861
; CHECK: otherexit:
878
- ; CHECK-NEXT: [[SUM_02_LCSSA:%.*]] = phi i32 [ [[RVAL_PH ]], [[OTHEREXIT_LOOPEXIT]] ], [ [[SUM_02_EPIL]], [[OTHEREXIT_LOOPEXIT3]] ]
862
+ ; CHECK-NEXT: [[SUM_02_LCSSA:%.*]] = phi i32 [ [[SUM_02 ]], [[OTHEREXIT_LOOPEXIT]] ], [ [[SUM_02_EPIL]], [[OTHEREXIT_LOOPEXIT3]] ]
879
863
; CHECK-NEXT: br label [[OTHEREXIT2:%.*]]
880
864
; CHECK: otherexit2:
881
865
; CHECK-NEXT: [[RVAL2:%.*]] = call i32 (...) @llvm.experimental.deoptimize.i32() [ "deopt"(i32 [[SUM_02_LCSSA]]) ]
0 commit comments