[RISCV] Fix crash in lowerVPSpliceExperimental with RV64LegalI32.

EVL1 will be i32 and not get type legalized to i64 so we need to
manually promote it to XLenVT.

Author: topperc

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -10824,6 +10824,9 @@ RISCVTargetLowering::lowerVPSpliceExperimental(SDValue Op,
     Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
   }
 
+  // EVL1 may need to be extended to XLenVT with RV64LegalI32.
+  EVL1 = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, EVL1);
+
   bool IsMaskVector = VT.getVectorElementType() == MVT::i1;
   if (IsMaskVector) {
     ContainerVT = ContainerVT.changeVectorElementType(MVT::i8);