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klensy
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klensy
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few additional fixes
1 parent b5bafe8 commit b9515a6

12 files changed

+41
-41
lines changed

‎mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -778,11 +778,11 @@ func.func @create_tensor_map(%devicePtr2d : memref<64x128xf32>, %devicePtr1d : m
778778
%crd0 = arith.constant 64 : index
779779
%crd1 = arith.constant 128 : index
780780
%devicePtr2d_unranked = memref.cast %devicePtr2d : memref<64x128xf32> to memref<*xf32>
781-
// CHECK : llvm.call @mgpuTensorMapEncodeTiledMemref
781+
// CHECK: llvm.call @mgpuTensorMapEncodeTiledMemref
782782
%tensorMap2d = nvgpu.tma.create.descriptor %devicePtr2d_unranked box[%crd0, %crd1] : memref<*xf32> -> !tensorMap2d
783783

784784
%devicePtr1d_unranked = memref.cast %devicePtr1d : memref<128xf32> to memref<*xf32>
785-
// CHECK : llvm.call @mgpuTensorMapEncodeTiledMemref
785+
// CHECK: llvm.call @mgpuTensorMapEncodeTiledMemref
786786
%tensorMap1d = nvgpu.tma.create.descriptor %devicePtr1d_unranked box[%crd1] : memref<*xf32> -> !tensorMap1d
787787
func.return
788788
}

‎mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ llvm.func @init_mbarrier(%barrier_gen : !llvm.ptr, %barrier : !llvm.ptr<3>, %cou
1717
llvm.func @init_mbarrier_arrive_expect_tx(%barrier : !llvm.ptr<3>, %txcount : i32, %pred : i1) {
1818
//CHECK: llvm.inline_asm has_side_effects asm_dialect = att "mbarrier.arrive.expect_tx.shared.b64 _, [$0], $1;", "r,r"
1919
nvvm.mbarrier.arrive.expect_tx.shared %barrier, %txcount : !llvm.ptr<3>, i32
20-
//CHECK : llvm.inline_asm has_side_effects asm_dialect = att "@$2 mbarrier.arrive.expect_tx.shared.b64 _, [$0], $1;", "r,r,b "
20+
//CHECK: llvm.inline_asm has_side_effects asm_dialect = att "@$2 mbarrier.arrive.expect_tx.shared.b64 _, [$0], $1;", "r,r,b "
2121
nvvm.mbarrier.arrive.expect_tx.shared %barrier, %txcount, predicate = %pred : !llvm.ptr<3>, i32, i1
2222
llvm.return
2323
}
@@ -129,7 +129,7 @@ func.func @tma_load_5d_all(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %bar
129129
func.func @tma_load_1d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier: !llvm.ptr<3>, %crd0: i32, %p : i1) {
130130
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "cp.async.bulk.tensor.1d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2} ], [$3];", "r,l,r,r"
131131
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0] : !llvm.ptr<3>, !llvm.ptr
132-
// CHECK : llvm.inline_asm has_side_effects asm_dialect = att "@$4 cp.async.bulk.tensor.1d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2} ], [$3];", "l,r,r,r,b"
132+
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "@$4 cp.async.bulk.tensor.1d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2} ], [$3];", "l,r,r,r,b"
133133
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0] predicate=%p : !llvm.ptr<3>, !llvm.ptr
134134
return
135135
}
@@ -138,7 +138,7 @@ func.func @tma_load_1d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier
138138
func.func @tma_load_2d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier: !llvm.ptr<3>, %crd0: i32, %crd1: i32, %p : i1) {
139139
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3} ], [$4];", "r,l,r,r,r"
140140
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0,%crd1] : !llvm.ptr<3>, !llvm.ptr
141-
// CHECK : llvm.inline_asm has_side_effects asm_dialect = att "@$5 cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3} ], [$4];", "l,r,r,r,r,b"
141+
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "@$5 cp.async.bulk.tensor.2d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3} ], [$4];", "l,r,r,r,r,b"
142142
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0,%crd1] predicate=%p : !llvm.ptr<3>, !llvm.ptr
143143
return
144144
}
@@ -147,7 +147,7 @@ func.func @tma_load_2d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier
147147
func.func @tma_load_3d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier: !llvm.ptr<3>, %crd0: i32, %crd1: i32, %crd2: i32, %p : i1) {
148148
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "cp.async.bulk.tensor.3d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4} ], [$5];", "r,l,r,r,r,r"
149149
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0,%crd1,%crd2] : !llvm.ptr<3>, !llvm.ptr
150-
// CHECK : llvm.inline_asm has_side_effects asm_dialect = att "@$6 cp.async.bulk.tensor.3d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4}], [$5];", "l,r,r,r,r,r,b"
150+
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "@$6 cp.async.bulk.tensor.3d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4}], [$5];", "l,r,r,r,r,r,b"
151151
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0,%crd1,%crd2] predicate=%p : !llvm.ptr<3>, !llvm.ptr
152152
return
153153
}
@@ -156,7 +156,7 @@ func.func @tma_load_3d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier
156156
func.func @tma_load_4d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier: !llvm.ptr<3>, %crd0: i32, %crd1: i32, %crd2: i32, %crd3: i32, %p : i1) {
157157
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "cp.async.bulk.tensor.4d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4,$5} ], [$6];", "r,l,r,r,r,r,r"
158158
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0,%crd1,%crd2,%crd3] : !llvm.ptr<3>, !llvm.ptr
159-
// CHECK : llvm.inline_asm has_side_effects asm_dialect = att "@$7 cp.async.bulk.tensor.4d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4,$5}], [$6];", "l,r,r,r,r,r,r,b"
159+
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "@$7 cp.async.bulk.tensor.4d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4,$5}], [$6];", "l,r,r,r,r,r,r,b"
160160
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0,%crd1,%crd2,%crd3] predicate=%p : !llvm.ptr<3>, !llvm.ptr
161161
return
162162
}
@@ -165,7 +165,7 @@ func.func @tma_load_4d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier
165165
func.func @tma_load_5d(%tmaDescriptor: !llvm.ptr, %dest : !llvm.ptr<3>, %barrier: !llvm.ptr<3>, %crd0: i32, %crd1: i32, %crd2: i32, %crd3: i32, %crd4: i32, %p : i1) {
166166
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "cp.async.bulk.tensor.5d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4,$5,$6} ], [$7];", "r,l,r,r,r,r,r,r"
167167
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0,%crd1,%crd2,%crd3,%crd4] : !llvm.ptr<3>, !llvm.ptr
168-
// CHECK : llvm.inline_asm has_side_effects asm_dialect = att "@$8 cp.async.bulk.tensor.5d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4,$5,$6}], [$7];", "l,r,r,r,r,r,r,r,b"
168+
// CHECK: llvm.inline_asm has_side_effects asm_dialect = att "@$8 cp.async.bulk.tensor.5d.shared::cluster.global.mbarrier::complete_tx::bytes [$0], [$1, {$2,$3,$4,$5,$6}], [$7];", "l,r,r,r,r,r,r,r,b"
169169
nvvm.cp.async.bulk.tensor.shared.cluster.global %dest, %tmaDescriptor, %barrier, box[%crd0,%crd1,%crd2,%crd3,%crd4] predicate=%p : !llvm.ptr<3>, !llvm.ptr
170170
return
171171
}

‎mlir/test/Conversion/SPIRVToLLVM/spirv-storage-class-mapping.mlir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,5 +91,5 @@ spirv.func @pointerCodeSectionINTEL(!spirv.ptr<i1, CodeSectionINTEL>) "None"
9191
spirv.func @pointerDeviceOnlyINTEL(!spirv.ptr<i1, DeviceOnlyINTEL>) "None"
9292

9393
// CHECK-OPENCL: llvm.func @pointerHostOnlyINTEL(!llvm.ptr<6>)
94-
// CHECK-UNKOWN: llvm.func @pointerHostOnlyINTEL(!llvm.ptr)
94+
// CHECK-UNKNOWN: llvm.func @pointerHostOnlyINTEL(!llvm.ptr)
9595
spirv.func @pointerHostOnlyINTEL(!spirv.ptr<i1, HostOnlyINTEL>) "None"

‎mlir/test/Dialect/ArmSME/tile-allocation-liveness.mlir

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -366,15 +366,15 @@ func.func @avoidable_spill(%a: vector<[4]xf32>, %b: vector<[4]xf32>, %c: vector<
366366

367367
// CHECK-LIVE-RANGE-LABEL: @cond_branch_with_backedge
368368
// CHECK-LIVE-RANGE: ^bb1:
369-
// CHECK-LIVE-RANGE--NEXT: ||| | arith.cmpi
370-
// CHECK-LIVE-RANGE--NEXT: EEE E cf.cond_br
369+
// CHECK-LIVE-RANGE-NEXT: ||| | arith.cmpi
370+
// CHECK-LIVE-RANGE-NEXT: EEE E cf.cond_br
371371
//
372-
// CHECK-LIVE-RANGE--NEXT: ^[[BB3_COPIES:[[:alnum:]]+]]:
373-
// CHECK-LIVE-RANGE--NEXT: ||| ES arm_sme.copy_tile
374-
// CHECK-LIVE-RANGE--NEXT: E|| |S arm_sme.copy_tile
375-
// CHECK-LIVE-RANGE--NEXT: E| ||S arm_sme.copy_tile
376-
// CHECK-LIVE-RANGE--NEXT: E |||S arm_sme.copy_tile
377-
// CHECK-LIVE-RANGE--NEXT: EEEE cf.br
372+
// CHECK-LIVE-RANGE-NEXT: ^[[BB3_COPIES:[[:alnum:]]+]]:
373+
// CHECK-LIVE-RANGE-NEXT: ||| ES arm_sme.copy_tile
374+
// CHECK-LIVE-RANGE-NEXT: E|| |S arm_sme.copy_tile
375+
// CHECK-LIVE-RANGE-NEXT: E| ||S arm_sme.copy_tile
376+
// CHECK-LIVE-RANGE-NEXT: E |||S arm_sme.copy_tile
377+
// CHECK-LIVE-RANGE-NEXT: EEEE cf.br
378378
//
379379
// It is important to note that the first three live ranges in ^bb1 do not end
380380
// at the `cf.cond_br` they are live-out via the backedge bb1 -> bb2 -> bb1.
@@ -389,15 +389,15 @@ func.func @avoidable_spill(%a: vector<[4]xf32>, %b: vector<[4]xf32>, %c: vector<
389389
//
390390
// CHECK-LIVE-RANGE: ========== Coalesced Live Ranges:
391391
// CHECK-LIVE-RANGE: ^bb1:
392-
// CHECK-LIVE-RANGE--NEXT: |||| arith.cmpi
393-
// CHECK-LIVE-RANGE--NEXT: EEEE cf.cond_br
392+
// CHECK-LIVE-RANGE-NEXT: |||| arith.cmpi
393+
// CHECK-LIVE-RANGE-NEXT: EEEE cf.cond_br
394394
//
395-
// CHECK-LIVE-RANGE--NEXT: ^[[BB3_COPIES]]:
396-
// CHECK-LIVE-RANGE--NEXT: |||| arm_sme.copy_tile
397-
// CHECK-LIVE-RANGE--NEXT: |||| arm_sme.copy_tile
398-
// CHECK-LIVE-RANGE--NEXT: |||| arm_sme.copy_tile
399-
// CHECK-LIVE-RANGE--NEXT: |||| arm_sme.copy_tile
400-
// CHECK-LIVE-RANGE--NEXT: EEEE cf.br
395+
// CHECK-LIVE-RANGE-NEXT: ^[[BB3_COPIES]]:
396+
// CHECK-LIVE-RANGE-NEXT: |||| arm_sme.copy_tile
397+
// CHECK-LIVE-RANGE-NEXT: |||| arm_sme.copy_tile
398+
// CHECK-LIVE-RANGE-NEXT: |||| arm_sme.copy_tile
399+
// CHECK-LIVE-RANGE-NEXT: |||| arm_sme.copy_tile
400+
// CHECK-LIVE-RANGE-NEXT: EEEE cf.br
401401

402402
// CHECK-LABEL: @cond_branch_with_backedge
403403
// CHECK-NOT: tile_id = 16

‎mlir/test/Dialect/LLVMIR/nvvm.mlir

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -466,22 +466,22 @@ llvm.func private @mbarrier_test_wait_shared(%barrier: !llvm.ptr<3>, %token : i6
466466

467467
// CHECK-LABEL: @wgmma_fence_aligned
468468
func.func @wgmma_fence_aligned() {
469-
// CHECK : nvvm.wgmma.fence.aligned
469+
// CHECK: nvvm.wgmma.fence.aligned
470470
nvvm.wgmma.fence.aligned
471471
return
472472
}
473473

474474
// CHECK-LABEL: @wgmma_commit_group_sync_aligned
475475
func.func @wgmma_commit_group_sync_aligned() {
476-
// CHECK : nvvm.wgmma.commit.group.sync.aligned
476+
// CHECK: nvvm.wgmma.commit.group.sync.aligned
477477
nvvm.wgmma.commit.group.sync.aligned
478478
return
479479
}
480480

481481

482482
// CHECK-LABEL: @wgmma_commit_group_sync_aligned
483483
func.func @wgmma_wait_group_sync_aligned() {
484-
// CHECK : nvvm.wgmma.wait.group.sync.aligned
484+
// CHECK: nvvm.wgmma.wait.group.sync.aligned
485485
nvvm.wgmma.wait.group.sync.aligned 0
486486
return
487487
}

‎mlir/test/Dialect/Linalg/data-layout-propagation.mlir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -795,7 +795,7 @@ func.func @reduction_pack_transpose_inner_dims(%arg0: tensor<128x256x32xi32>,
795795
// CHECK-SAME: %[[ARG1:[a-zA-Z0-9]+]]
796796
// CHECK: %[[ARG1_EMPTY:.+]] = tensor.empty() : tensor<4x16x16x32xi32>
797797
// CHECK: %[[PACK_ARG1:.+]] = tensor.pack %[[ARG1]]
798-
// CHECK-SME: inner_dims_pos = [1, 0] inner_tiles = [16, 32]
798+
// CHECK-SAME: inner_dims_pos = [1, 0] inner_tiles = [16, 32]
799799
// CHECK-SAME: into %[[ARG1_EMPTY]]
800800
// CHECK: %[[ARG0_EMPTY:.+]] = tensor.empty() : tensor<4x16x32x16x32xi32>
801801
// CHECK: %[[PACK_ARG0:.+]] = tensor.pack %[[ARG0]]

‎mlir/test/Dialect/SPIRV/IR/logical-ops.mlir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -180,47 +180,47 @@ func.func @logicalUnary(%arg0 : i32)
180180
func.func @select_op_bool(%arg0: i1) -> () {
181181
%0 = spirv.Constant true
182182
%1 = spirv.Constant false
183-
// CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i1
183+
// CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i1
184184
%2 = spirv.Select %arg0, %0, %1 : i1, i1
185185
return
186186
}
187187

188188
func.func @select_op_int(%arg0: i1) -> () {
189189
%0 = spirv.Constant 2 : i32
190190
%1 = spirv.Constant 3 : i32
191-
// CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i32
191+
// CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i32
192192
%2 = spirv.Select %arg0, %0, %1 : i1, i32
193193
return
194194
}
195195

196196
func.func @select_op_float(%arg0: i1) -> () {
197197
%0 = spirv.Constant 2.0 : f32
198198
%1 = spirv.Constant 3.0 : f32
199-
// CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, f32
199+
// CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, f32
200200
%2 = spirv.Select %arg0, %0, %1 : i1, f32
201201
return
202202
}
203203

204204
func.func @select_op_ptr(%arg0: i1) -> () {
205205
%0 = spirv.Variable : !spirv.ptr<f32, Function>
206206
%1 = spirv.Variable : !spirv.ptr<f32, Function>
207-
// CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, !spirv.ptr<f32, Function>
207+
// CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, !spirv.ptr<f32, Function>
208208
%2 = spirv.Select %arg0, %0, %1 : i1, !spirv.ptr<f32, Function>
209209
return
210210
}
211211

212212
func.func @select_op_vec(%arg0: i1) -> () {
213213
%0 = spirv.Constant dense<[2.0, 3.0, 4.0]> : vector<3xf32>
214214
%1 = spirv.Constant dense<[5.0, 6.0, 7.0]> : vector<3xf32>
215-
// CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, vector<3xf32>
215+
// CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, vector<3xf32>
216216
%2 = spirv.Select %arg0, %0, %1 : i1, vector<3xf32>
217217
return
218218
}
219219

220220
func.func @select_op_vec_condn_vec(%arg0: vector<3xi1>) -> () {
221221
%0 = spirv.Constant dense<[2.0, 3.0, 4.0]> : vector<3xf32>
222222
%1 = spirv.Constant dense<[5.0, 6.0, 7.0]> : vector<3xf32>
223-
// CHECK : spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : vector<3xi1>, vector<3xf32>
223+
// CHECK: spirv.Select {{%.*}}, {{%.*}}, {{%.*}} : vector<3xi1>, vector<3xf32>
224224
%2 = spirv.Select %arg0, %0, %1 : vector<3xi1>, vector<3xf32>
225225
return
226226
}

‎mlir/test/Dialect/SPIRV/IR/structure-ops.mlir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -330,7 +330,7 @@ spirv.module Logical GLSL450 {
330330
// TODO: Fix test case after initialization with normal constant is addressed
331331
// spirv.module Logical GLSL450 {
332332
// %0 = spirv.Constant 4.0 : f32
333-
// // CHECK1: spirv.Variable init(%0) : !spirv.ptr<f32, Private>
333+
// COM: CHECK: spirv.Variable init(%0) : !spirv.ptr<f32, Private>
334334
// spirv.GlobalVariable @var1 init(%0) : !spirv.ptr<f32, Private>
335335
// }
336336

@@ -372,7 +372,7 @@ spirv.module Logical GLSL450 {
372372
// TODO: Fix test case after initialization with constant is addressed
373373
// spirv.module Logical GLSL450 {
374374
// %0 = spirv.Constant 4.0 : f32
375-
// // CHECK1: spirv.GlobalVariable @var1 initializer(%0) {binding = 5 : i32} : !spirv.ptr<f32, Private>
375+
// COM: CHECK: spirv.GlobalVariable @var1 initializer(%0) {binding = 5 : i32} : !spirv.ptr<f32, Private>
376376
// spirv.GlobalVariable @var1 initializer(%0) {binding = 5 : i32} : !spirv.ptr<f32, Private>
377377
// }
378378

‎mlir/test/Dialect/Tensor/fold-into-pack-and-unpack.mlir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -544,7 +544,7 @@ func.func @linalg_transpose_tensor_unpack_fold(%arg0: tensor<1x1x4x16xi32>) -> t
544544
// CHECK-SAME: outer_dims_perm = [1, 0]
545545
// CHECK-SAME: inner_dims_pos = [1, 0]
546546
// CHECK-SAME: inner_tiles = [4, 16]
547-
// CHEKC-SAME: into %[[OUT]] : tensor<1x1x4x16xi32> -> tensor<16x4xi32>
547+
// CHECK-SAME: into %[[OUT]] : tensor<1x1x4x16xi32> -> tensor<16x4xi32>
548548
// CHECK: return %[[UNPACK]] : tensor<16x4xi32>
549549
// CHECK: }
550550

‎mlir/test/Target/LLVMIR/Import/metadata-loop.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -324,7 +324,7 @@ end:
324324
; // -----
325325

326326
; Verify the unused access group is not imported.
327-
; CHECK-COUNT1: #llvm.access_group
327+
; CHECK-COUNT-1: #llvm.access_group
328328

329329
; CHECK-LABEL: @unused_parallel_access
330330
define void @unused_parallel_access(ptr %arg) {

‎mlir/test/Target/LLVMIR/omptarget-array-sectioning-host.mlir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ module attributes {omp.is_target_device = false} {
4242

4343
// CHECK: @.offload_sizes = private unnamed_addr constant [2 x i64] [i64 36, i64 108]
4444
// CHECK: @.offload_maptypes = private unnamed_addr constant [2 x i64] [i64 35, i64 35]
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// CHECKL: @.offload_mapnames = private constant [2 x ptr] [ptr @0, ptr @1]
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// CHECK: @.offload_mapnames = private constant [2 x ptr] [ptr @0, ptr @1]
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// CHECK: define void @_3d_target_array_section()
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‎mlir/test/python/dialects/transform_structured_ext.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -443,7 +443,7 @@ def testTileExplicitLoopTypeAll(target):
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structured.TileUsingForOp(types, target, sizes=[2, 3, 4])
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# CHECK-LABEL: TEST: testTileExplicitLoopTypeAll
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# CHECK: = transform.structured.tile
446-
# CHECK-SAME : (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">,
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# CHECK-SAME: (!transform.any_op) -> (!transform.any_op, !transform.op<"scf.for">,
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# CHECK-SAME: !transform.op<"scf.parallel">, !transform.op<"scf.forall">
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