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Xtensa
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8 files changed

+66
-75
lines changed

8 files changed

+66
-75
lines changed

llvm/lib/Target/Xtensa/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
13+
tablegen(LLVM XtensaGenSDNodeInfo.inc -gen-sd-node-info)
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tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget)
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1516
add_public_tablegen_target(XtensaCommonTableGen)
@@ -22,6 +23,7 @@ add_llvm_target(XtensaCodeGen
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XtensaISelDAGToDAG.cpp
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XtensaISelLowering.cpp
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XtensaRegisterInfo.cpp
26+
XtensaSelectionDAGInfo.cpp
2527
XtensaSubtarget.cpp
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XtensaTargetMachine.cpp
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llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp

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@@ -12,6 +12,7 @@
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#include "MCTargetDesc/XtensaMCTargetDesc.h"
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#include "Xtensa.h"
15+
#include "XtensaSelectionDAGInfo.h"
1516
#include "XtensaTargetMachine.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"

llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

Lines changed: 1 addition & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
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#include "XtensaConstantPoolValue.h"
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#include "XtensaInstrInfo.h"
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#include "XtensaMachineFunctionInfo.h"
18+
#include "XtensaSelectionDAGInfo.h"
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#include "XtensaSubtarget.h"
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#include "XtensaTargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
@@ -1287,34 +1288,6 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
12871288
}
12881289
}
12891290

1290-
const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
1291-
switch (Opcode) {
1292-
case XtensaISD::BR_JT:
1293-
return "XtensaISD::BR_JT";
1294-
case XtensaISD::CALL:
1295-
return "XtensaISD::CALL";
1296-
case XtensaISD::CALLW8:
1297-
return "XtensaISD::CALLW8";
1298-
case XtensaISD::EXTUI:
1299-
return "XtensaISD::EXTUI";
1300-
case XtensaISD::MOVSP:
1301-
return "XtensaISD::MOVSP";
1302-
case XtensaISD::PCREL_WRAPPER:
1303-
return "XtensaISD::PCREL_WRAPPER";
1304-
case XtensaISD::RET:
1305-
return "XtensaISD::RET";
1306-
case XtensaISD::RETW:
1307-
return "XtensaISD::RETW";
1308-
case XtensaISD::SELECT_CC:
1309-
return "XtensaISD::SELECT_CC";
1310-
case XtensaISD::SRCL:
1311-
return "XtensaISD::SRCL";
1312-
case XtensaISD::SRCR:
1313-
return "XtensaISD::SRCR";
1314-
}
1315-
return nullptr;
1316-
}
1317-
13181291
//===----------------------------------------------------------------------===//
13191292
// Custom insertion
13201293
//===----------------------------------------------------------------------===//

llvm/lib/Target/Xtensa/XtensaISelLowering.h

Lines changed: 0 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -20,45 +20,6 @@
2020

2121
namespace llvm {
2222

23-
namespace XtensaISD {
24-
enum {
25-
FIRST_NUMBER = ISD::BUILTIN_OP_END,
26-
BR_JT,
27-
28-
// Calls a function. Operand 0 is the chain operand and operand 1
29-
// is the target address. The arguments start at operand 2.
30-
// There is an optional glue operand at the end.
31-
CALL,
32-
// Call with rotation window by 8 registers
33-
CALLW8,
34-
35-
// Extract unsigned immediate. Operand 0 is value, operand 1
36-
// is bit position of the field [0..31], operand 2 is bit size
37-
// of the field [1..16]
38-
EXTUI,
39-
40-
MOVSP,
41-
42-
// Wraps a TargetGlobalAddress that should be loaded using PC-relative
43-
// accesses. Operand 0 is the address.
44-
PCREL_WRAPPER,
45-
RET,
46-
RETW,
47-
48-
// Select with condition operator - This selects between a true value and
49-
// a false value (ops #2 and #3) based on the boolean result of comparing
50-
// the lhs and rhs (ops #0 and #1) of a conditional expression with the
51-
// condition code in op #4
52-
SELECT_CC,
53-
54-
// SRCL(R) performs shift left(right) of the concatenation of 2 registers
55-
// and returns high(low) 32-bit part of 64-bit result
56-
SRCL,
57-
// Shift Right Combined
58-
SRCR,
59-
};
60-
}
61-
6223
class XtensaSubtarget;
6324

6425
class XtensaTargetLowering : public TargetLowering {
@@ -79,8 +40,6 @@ class XtensaTargetLowering : public TargetLowering {
7940

8041
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
8142

82-
const char *getTargetNodeName(unsigned Opcode) const override;
83-
8443
std::pair<unsigned, const TargetRegisterClass *>
8544
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
8645
StringRef Constraint, MVT VT) const override;
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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
//===- XtensaSelectionDAGInfo.cpp -----------------------------------------===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
#include "XtensaSelectionDAGInfo.h"
10+
11+
#define GET_SDNODE_DESC
12+
#include "XtensaGenSDNodeInfo.inc"
13+
14+
using namespace llvm;
15+
16+
XtensaSelectionDAGInfo::XtensaSelectionDAGInfo()
17+
: SelectionDAGGenTargetInfo(XtensaGenSDNodeInfo) {}
18+
19+
XtensaSelectionDAGInfo::~XtensaSelectionDAGInfo() = default;
Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
//===- XtensaSelectionDAGInfo.h ---------------------------------*- C++ -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
9+
#ifndef LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H
10+
#define LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H
11+
12+
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
13+
14+
#define GET_SDNODE_ENUM
15+
#include "XtensaGenSDNodeInfo.inc"
16+
17+
namespace llvm {
18+
19+
class XtensaSelectionDAGInfo : public SelectionDAGGenTargetInfo {
20+
public:
21+
XtensaSelectionDAGInfo();
22+
23+
~XtensaSelectionDAGInfo() override;
24+
};
25+
26+
} // namespace llvm
27+
28+
#endif // LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H

llvm/lib/Target/Xtensa/XtensaSubtarget.cpp

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
//===----------------------------------------------------------------------===//
1212

1313
#include "XtensaSubtarget.h"
14+
#include "XtensaSelectionDAGInfo.h"
1415
#include "llvm/IR/GlobalValue.h"
1516
#include "llvm/Support/Debug.h"
1617

@@ -39,4 +40,12 @@ XtensaSubtarget::XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
3940
const TargetMachine &TM)
4041
: XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT),
4142
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
42-
TSInfo(), FrameLowering(*this) {}
43+
FrameLowering(*this) {
44+
TSInfo = std::make_unique<SelectionDAGTargetInfo>();
45+
}
46+
47+
XtensaSubtarget::~XtensaSubtarget() = default;
48+
49+
const SelectionDAGTargetInfo *XtensaSubtarget::getSelectionDAGInfo() const {
50+
return TSInfo.get();
51+
}

llvm/lib/Target/Xtensa/XtensaSubtarget.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@
1717
#include "XtensaISelLowering.h"
1818
#include "XtensaInstrInfo.h"
1919
#include "XtensaRegisterInfo.h"
20-
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
2120
#include "llvm/CodeGen/TargetSubtargetInfo.h"
2221
#include "llvm/IR/DataLayout.h"
2322
#include "llvm/Target/TargetMachine.h"
@@ -38,7 +37,7 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
3837
const Triple &TargetTriple;
3938
XtensaInstrInfo InstrInfo;
4039
XtensaTargetLowering TLInfo;
41-
SelectionDAGTargetInfo TSInfo;
40+
std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
4241
XtensaFrameLowering FrameLowering;
4342

4443
XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
@@ -47,6 +46,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
4746
XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
4847
const TargetMachine &TM);
4948

49+
~XtensaSubtarget() override;
50+
5051
const Triple &getTargetTriple() const { return TargetTriple; }
5152

5253
const TargetFrameLowering *getFrameLowering() const override {
@@ -60,9 +61,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
6061
const XtensaTargetLowering *getTargetLowering() const override {
6162
return &TLInfo;
6263
}
63-
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
64-
return &TSInfo;
65-
}
64+
65+
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
6666

6767
bool hasDensity() const { return HasDensity; }
6868
bool hasMAC16() const { return HasMAC16; }

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