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davemgreendavemgreen
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Cleanup
1 parent 6f1afaa commit bfb6753

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11 files changed

+42
-63
lines changed

11 files changed

+42
-63
lines changed

‎llvm/include/llvm/Analysis/MemoryLocation.h

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -291,23 +291,12 @@ class MemoryLocation {
291291
return MemoryLocation(Ptr, LocationSize::beforeOrAfterPointer(), AATags);
292292
}
293293

294-
// TODO: Remove getSizeOrUnknown
295-
// interface once llvm/unittests/CodeGen/SelectionDAGAddressAnalysisTest is
296-
// updated
297-
static uint64_t getSizeOrUnknown(const TypeSize &T) {
298-
return T.isScalable() ? UnknownSize : T.getFixedValue();
299-
}
300-
301294
MemoryLocation() : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()) {}
302295

303296
explicit MemoryLocation(const Value *Ptr, LocationSize Size,
304297
const AAMDNodes &AATags = AAMDNodes())
305298
: Ptr(Ptr), Size(Size), AATags(AATags) {}
306299

307-
explicit MemoryLocation(const Value *Ptr, TypeSize Size,
308-
const AAMDNodes &AATags = AAMDNodes())
309-
: Ptr(Ptr), Size(LocationSize::precise(Size)), AATags(AATags) {}
310-
311300
MemoryLocation getWithNewPtr(const Value *NewPtr) const {
312301
MemoryLocation Copy(*this);
313302
Copy.Ptr = NewPtr;

‎llvm/include/llvm/CodeGen/MachineFunction.h

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1033,8 +1033,8 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10331033
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
10341034

10351035
MachineMemOperand *getMachineMemOperand(
1036-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, TypeSize ts,
1037-
Align base_alignment, const AAMDNodes &AAInfo = AAMDNodes(),
1036+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize TS,
1037+
Align BaseAlignment, const AAMDNodes &AAInfo = AAMDNodes(),
10381038
const MDNode *Ranges = nullptr, SyncScope::ID SSID = SyncScope::System,
10391039
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
10401040
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
@@ -1059,14 +1059,12 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10591059
}
10601060

10611061
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
1062-
int64_t Offset, TypeSize ts) {
1062+
int64_t Offset, TypeSize TS) {
10631063
return getMachineMemOperand(
10641064
MMO, Offset,
1065-
ts.getKnownMinValue() == ~UINT64_C(0)
1066-
? LLT()
1067-
: ts.isScalable()
1068-
? LLT::scalable_vector(1, 8 * ts.getKnownMinValue())
1069-
: LLT::scalar(8 * ts.getKnownMinValue()));
1065+
TS.getKnownMinValue() == ~UINT64_C(0) ? LLT()
1066+
: TS.isScalable() ? LLT::scalable_vector(1, 8 * TS.getKnownMinValue())
1067+
: LLT::scalar(8 * TS.getKnownMinValue()));
10701068
}
10711069

10721070
/// getMachineMemOperand - Allocate a new MachineMemOperand by copying
@@ -1078,7 +1076,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction {
10781076
uint64_t Size);
10791077
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10801078
const MachinePointerInfo &PtrInfo,
1081-
TypeSize ts);
1079+
TypeSize TS);
10821080
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
10831081
const MachinePointerInfo &PtrInfo,
10841082
LLT Ty);

‎llvm/include/llvm/CodeGen/MachineMemOperand.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -192,7 +192,7 @@ class MachineMemOperand {
192192
SyncScope::ID SSID = SyncScope::System,
193193
AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
194194
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
195-
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, TypeSize ts,
195+
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, TypeSize TS,
196196
Align a, const AAMDNodes &AAInfo = AAMDNodes(),
197197
const MDNode *Ranges = nullptr,
198198
SyncScope::ID SSID = SyncScope::System,

‎llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -252,7 +252,7 @@ bool GISelAddressing::instMayAlias(const MachineInstr &MI,
252252
return false;
253253
}
254254

255-
// if NumBytes is scalable and offset is not 0, conservatively return may
255+
// If NumBytes is scalable and offset is not 0, conservatively return may
256256
// alias
257257
if ((MUC0.NumBytes.isScalable() && (MUC0.Offset != 0)) ||
258258
(MUC1.NumBytes.isScalable() && (MUC1.Offset != 0)))

‎llvm/lib/CodeGen/MachineFunction.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -494,12 +494,12 @@ MachineMemOperand *MachineFunction::getMachineMemOperand(
494494
}
495495

496496
MachineMemOperand *MachineFunction::getMachineMemOperand(
497-
MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, TypeSize ts,
498-
Align base_alignment, const AAMDNodes &AAInfo, const MDNode *Ranges,
497+
MachinePointerInfo PtrInfo, MachineMemOperand::Flags F, TypeSize TS,
498+
Align BaseAlignment, const AAMDNodes &AAInfo, const MDNode *Ranges,
499499
SyncScope::ID SSID, AtomicOrdering Ordering,
500500
AtomicOrdering FailureOrdering) {
501501
return new (Allocator)
502-
MachineMemOperand(PtrInfo, f, ts, base_alignment, AAInfo, Ranges, SSID,
502+
MachineMemOperand(PtrInfo, F, TS, BaseAlignment, AAInfo, Ranges, SSID,
503503
Ordering, FailureOrdering);
504504
}
505505

@@ -524,9 +524,9 @@ MachineMemOperand *MachineFunction::getMachineMemOperand(
524524
MachineMemOperand *
525525
MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
526526
const MachinePointerInfo &PtrInfo,
527-
TypeSize ts) {
527+
TypeSize TS) {
528528
return new (Allocator)
529-
MachineMemOperand(PtrInfo, MMO->getFlags(), ts, MMO->getBaseAlign(),
529+
MachineMemOperand(PtrInfo, MMO->getFlags(), TS, MMO->getBaseAlign(),
530530
AAMDNodes(), nullptr, MMO->getSyncScopeID(),
531531
MMO->getSuccessOrdering(), MMO->getFailureOrdering());
532532
}

‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1342,10 +1342,9 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
13421342

13431343
// If Scalable Location Size has non-zero offset,
13441344
// Width + Offset does not work at the moment
1345-
if ((WidthA.isScalable() && (OffsetA > 0)) ||
1346-
(WidthB.isScalable() && (OffsetB > 0))) {
1345+
if ((WidthA.isScalable() && OffsetA > 0) ||
1346+
(WidthB.isScalable() && OffsetB > 0))
13471347
return true;
1348-
}
13491348

13501349
int64_t OverlapA = KnownWidthA
13511350
? WidthA.getKnownMinValue() + OffsetA - MinOffset

‎llvm/lib/CodeGen/MachineOperand.cpp

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1111,20 +1111,18 @@ MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
11111111
s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
11121112
AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
11131113

1114-
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1115-
TypeSize ts, Align a,
1114+
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags F,
1115+
TypeSize TS, Align BaseAlignment,
11161116
const AAMDNodes &AAInfo,
11171117
const MDNode *Ranges, SyncScope::ID SSID,
11181118
AtomicOrdering Ordering,
11191119
AtomicOrdering FailureOrdering)
11201120
: MachineMemOperand(
1121-
ptrinfo, f,
1122-
ts.getKnownMinValue() == ~UINT64_C(0)
1123-
? LLT()
1124-
: ts.isScalable()
1125-
? LLT::scalable_vector(1, 8 * ts.getKnownMinValue())
1126-
: LLT::scalar(8 * ts.getKnownMinValue()),
1127-
a, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1121+
ptrinfo, F,
1122+
TS.getKnownMinValue() == ~UINT64_C(0) ? LLT()
1123+
: TS.isScalable() ? LLT::scalable_vector(1, 8 * TS.getKnownMinValue())
1124+
: LLT::scalar(8 * TS.getKnownMinValue()),
1125+
BaseAlignment, AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
11281126

11291127
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
11301128
// The Value and Offset may differ due to CSE. But the flags and size

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 11 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -27916,20 +27916,17 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2791627916
return false;
2791727917
}
2791827918

27919-
// if NumBytes is scalable and offset is not 0, conservatively return may
27919+
// If NumBytes is scalable and offset is not 0, conservatively return may
2792027920
// alias
2792127921
if ((MUC0.NumBytes.hasValue() && MUC0.NumBytes.isScalable() &&
27922-
(MUC0.Offset != 0)) ||
27922+
MUC0.Offset != 0) ||
2792327923
(MUC1.NumBytes.hasValue() && MUC1.NumBytes.isScalable() &&
27924-
(MUC1.Offset != 0)))
27924+
MUC1.Offset != 0))
2792527925
return true;
2792627926
// Try to prove that there is aliasing, or that there is no aliasing. Either
2792727927
// way, we can return now. If nothing can be proved, proceed with more tests.
27928-
const bool BothNotScalable = !(MUC0.NumBytes.isScalable() ||
27929-
MUC1.NumBytes.isScalable());
2793027928
bool IsAlias;
27931-
if (BothNotScalable &&
27932-
BaseIndexOffset::computeAliasing(Op0, MUC0.NumBytes, Op1, MUC1.NumBytes,
27929+
if (BaseIndexOffset::computeAliasing(Op0, MUC0.NumBytes, Op1, MUC1.NumBytes,
2793327930
DAG, IsAlias))
2793427931
return IsAlias;
2793527932

@@ -27957,22 +27954,18 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2795727954
LocationSize Size0 = MUC0.NumBytes;
2795827955
LocationSize Size1 = MUC1.NumBytes;
2795927956

27960-
if (BothNotScalable) {
27961-
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 &&
27962-
Size0.hasValue() && Size1.hasValue() && !Size0.isScalable() &&
27963-
!Size1.isScalable() && Size0.getValue() == Size1.getValue() &&
27964-
OrigAlignment0 > Size0.getValue() &&
27965-
SrcValOffset0 % Size0.getValue() == 0 &&
27966-
SrcValOffset1 % Size1.getValue() == 0) {
27967-
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value();
27968-
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value();
27957+
if (OrigAlignment0 == OrigAlignment1 && SrcValOffset0 != SrcValOffset1 &&
27958+
Size0.hasValue() && Size1.hasValue() && !Size0.isScalable() &&
27959+
!Size1.isScalable() && Size0.getValue() == Size1.getValue() && OrigAlignment0 > Size0.getValue() &&
27960+
SrcValOffset0 % Size0.getValue() == 0 && SrcValOffset1 % Size1.getValue() == 0) {
27961+
int64_t OffAlign0 = SrcValOffset0 % OrigAlignment0.value();
27962+
int64_t OffAlign1 = SrcValOffset1 % OrigAlignment1.value();
2796927963

2797027964
// There is no overlap between these relatively aligned accesses of
2797127965
// similar size. Return no alias.
2797227966
if ((OffAlign0 + Size0.getValue()) <= OffAlign1 ||
2797327967
(OffAlign1 + Size1.getValue()) <= OffAlign0)
2797427968
return false;
27975-
}
2797627969
}
2797727970

2797827971
bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
@@ -27995,7 +27988,7 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2799527988
LocationSize Loc0 = Size0.getValue().isScalable()
2799627989
? LocationSize::precise(Size0.getValue())
2799727990
: LocationSize::precise(Overlap0);
27998-
LocationSize Loc1 = Size1.getValue().isScalable()
27991+
LocationSize Loc1 = Size1.isScalable()
2799927992
? LocationSize::precise(Size1.getValue())
2800027993
: LocationSize::precise(Overlap1);
2800127994
if (AA->isNoAlias(

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11712,9 +11712,9 @@ MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1171211712
// We check here that the size of the memory operand fits within the size of
1171311713
// the MMO. This is because the MMO might indicate only a possible address
1171411714
// range instead of specifying the affected memory addresses precisely.
11715-
if (MMO->getType().isValid())
11716-
assert(TypeSize::isKnownLE(memvt.getStoreSize(), MMO->getSize()) &&
11717-
"Size mismatch!");
11715+
assert((!MMO->getType().isValid() ||
11716+
TypeSize::isKnownLE(memvt.getStoreSize(), MMO->getSize())) &&
11717+
"Size mismatch!");
1171811718
}
1171911719

1172011720
/// Profile - Gather unique data for the node.

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3550,7 +3550,7 @@ bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode *N) const {
35503550
if (N->isDivergent() && !AMDGPUInstrInfo::isUniformMMO(MMO))
35513551
return false;
35523552

3553-
return Ld->getAlign() >= Align(std::min(MMO->getSize(), uint64_t(4))) &&
3553+
return Ld->getAlign() >= Align(std::min(MMO->getSize().getKnownMinValue(), uint64_t(4))) &&
35543554
((Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
35553555
Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ||
35563556
(Subtarget->getScalarizeGlobalBehavior() &&

‎llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -172,14 +172,16 @@ bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
172172
if (!MMO.getValue())
173173
return true;
174174

175-
MemoryLocation L(MMO.getValue(), MMO.getSize(), MMO.getAAInfo());
175+
MemoryLocation L(MMO.getValue(), MMO.getSize().getFixedValue(),
176+
MMO.getAAInfo());
176177

177178
for (auto *SI : Stores) {
178179
const MachineMemOperand &SMO = getStoreTarget(SI);
179180
if (!SMO.getValue())
180181
return true;
181182

182-
MemoryLocation SL(SMO.getValue(), SMO.getSize(), SMO.getAAInfo());
183+
MemoryLocation SL(SMO.getValue(), SMO.getSize().getFixedValue(),
184+
SMO.getAAInfo());
183185
if (!AA->isNoAlias(L, SL))
184186
return true;
185187
}

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