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[AMDGPU][True16][MC] added fake16 for gfx12 alias MC test (#120624)
This is a NFC. Duplicate gfx12_asm_vop3_alias.s file to true16/fake16 version and update `real-true16` flag on it. This is preparing the upcoming changes for true16
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// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
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v_min3_f32 v5, v1, v2, v3
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// GFX12: v_min3_num_f32 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x29,0xd6,0x01,0x05,0x0e,0x04]
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v_max3_f32 v5, v1, v2, v3
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// GFX12: v_max3_num_f32 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x2a,0xd6,0x01,0x05,0x0e,0x04]
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v_min3_f16 v5, v1, v2, v3
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// GFX12: v_min3_num_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x2b,0xd6,0x01,0x05,0x0e,0x04]
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v_max3_f16 v5, v1, v2, v3
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// GFX12: v_max3_num_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x2c,0xd6,0x01,0x05,0x0e,0x04]
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v_med3_f32 v5, v1, v2, v3
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// GFX12: v_med3_num_f32 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x31,0xd6,0x01,0x05,0x0e,0x04]
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v_med3_f16 v5, v1, v2, v3
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// GFX12: v_med3_num_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x32,0xd6,0x01,0x05,0x0e,0x04]
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v_minmax_f32_e64_dpp v0, -v1, -v2, -v3 dpp8:[0,1,2,3,4,5,6,7]
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// GFX12: v_minmax_num_f32_e64_dpp v0, -v1, -v2, -v3 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x00,0x68,0xd6,0xe9,0x04,0x0e,0xe4,0x01,0x88,0xc6,0xfa]
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v_maxmin_f32_e64_dpp v0, v1, v2, v3 clamp dpp8:[0,1,2,3,4,5,6,7]
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// GFX12: v_maxmin_num_f32_e64_dpp v0, v1, v2, v3 clamp dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0x00,0x80,0x69,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0xc6,0xfa]
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v_minmax_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
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// GFX12: v_minmax_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
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v_maxmin_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0]
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// GFX12: v_maxmin_num_f16_e64_dpp v5, v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x6b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
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v_mad_i64_i32 v[5:6], s12, v1, v2, v[3:4]
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// GFX12: v_mad_co_i64_i32 v[5:6], s12, v1, v2, v[3:4] ; encoding: [0x05,0x0c,0xff,0xd6,0x01,0x05,0x0e,0x04]
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v_mad_u64_u32 v[5:6], s12, v1, v2, v[3:4]
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// GFX12: v_mad_co_u64_u32 v[5:6], s12, v1, v2, v[3:4] ; encoding: [0x05,0x0c,0xfe,0xd6,0x01,0x05,0x0e,0x04]
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v_max_f64 v[5:6], s[2:3], s[4:5]
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// GFX12: v_max_num_f64_e64 v[5:6], s[2:3], s[4:5] ; encoding: [0x05,0x00,0x0e,0xd5,0x02,0x08,0x00,0x00]
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v_min_f64 v[5:6], s[2:3], s[4:5]
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// GFX12: v_min_num_f64_e64 v[5:6], s[2:3], s[4:5] ; encoding: [0x05,0x00,0x0d,0xd5,0x02,0x08,0x00,0x00]
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v_cvt_pknorm_i16_f16 v5, v1, v2
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// GFX12: v_cvt_pk_norm_i16_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
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v_cvt_pknorm_u16_f16 v5, v1, v2
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// GFX12: v_cvt_pk_norm_u16_f16 v5, v1, v2 ; encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
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v_add3_nc_u32 v5, v1, v2, s3
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// GFX12: v_add3_u32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]
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v_xor_add_u32 v5, v1, v2, s3
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// GFX12: v_xad_u32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x45,0xd6,0x01,0x05,0x0e,0x00]

llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s

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// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
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// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
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v_min3_f32 v5, v1, v2, v3
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// GFX12: v_min3_num_f32 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x29,0xd6,0x01,0x05,0x0e,0x04]

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