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9 | 9 | # CHECK-NEXT: 0x0 R_RISCV_SUB64 w 0x0
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10 | 10 | # CHECK-NEXT: 0x8 R_RISCV_ADD64 w 0x0
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11 | 11 | # CHECK-NEXT: 0x8 R_RISCV_SUB64 extern 0x0
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| 12 | +# CHECK-NEXT: 0x10 R_RISCV_ADD32 x 0x0 |
| 13 | +# CHECK-NEXT: 0x10 R_RISCV_SUB32 w 0x0 |
| 14 | +# CHECK-NEXT: 0x14 R_RISCV_ADD32 w1 0x0 |
| 15 | +# CHECK-NEXT: 0x14 R_RISCV_SUB32 w 0x0 |
| 16 | +# CHECK-NEXT: 0x18 R_RISCV_ADD32 .L.str 0x0 |
| 17 | +# CHECK-NEXT: 0x18 R_RISCV_SUB32 w 0x0 |
12 | 18 | # CHECK-NEXT: }
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13 | 19 | # CHECK-NEXT: Section ({{.*}}) .rela.alloc_x {
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14 | 20 | # CHECK-NEXT: 0x0 R_RISCV_ADD64 y 0x0
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34 | 40 | .endif
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35 | 41 |
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36 | 42 | .section .alloc_w,"aw",@progbits; w:
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37 |
| -.quad extern-w |
| 43 | +.quad extern-w # extern is undefined |
38 | 44 | .quad w-extern
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| 45 | +.long x-w # A is later defined in another section |
| 46 | +.long w1-w # A is later defined in the same section |
| 47 | +.long .L.str-w # A is temporary |
| 48 | +w1: |
| 49 | + |
39 | 50 | .section .alloc_x,"aw",@progbits; x:
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40 | 51 | .quad y-x
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41 | 52 | .section .alloc_y,"aw",@progbits; y:
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56 | 67 | .section .nonalloc_y; ny:
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57 | 68 | .quad nx-ny
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58 | 69 |
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| 70 | +## -gdwarf-aranges generated assembly expects no relocation. |
| 71 | +## Otherwise, a .Lsec_end0 symbol (defined at the end of .rodata.str1.1) |
| 72 | +## will be rejected by linkers. |
| 73 | +.section .rodata.str1.1,"aMS",@progbits,1 |
| 74 | +.L.str: |
| 75 | + .asciz "hello" |
| 76 | +.section .rodata.str1.1,"aMS",@progbits,1 |
| 77 | +.Lsec_end0: |
| 78 | +.section .debug_aranges,"",@progbits |
| 79 | +.quad .Lsec_end0-.L.str |
| 80 | + |
59 | 81 | ## .apple_names/.apple_types are fixed-size and do not need fixups.
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60 | 82 | ## llvm-dwarfdump --apple-names does not process R_RISCV_{ADD,SUB}32 in them.
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61 | 83 | ## See llvm/test/DebugInfo/Generic/accel-table-hash-collisions.ll
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