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[test] Add some interesting cases to MC/RISCV/riscv64-64b-pcrel.s
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llvm/test/MC/RISCV/riscv64-64b-pcrel.s

Lines changed: 23 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,12 @@
99
# CHECK-NEXT: 0x0 R_RISCV_SUB64 w 0x0
1010
# CHECK-NEXT: 0x8 R_RISCV_ADD64 w 0x0
1111
# CHECK-NEXT: 0x8 R_RISCV_SUB64 extern 0x0
12+
# CHECK-NEXT: 0x10 R_RISCV_ADD32 x 0x0
13+
# CHECK-NEXT: 0x10 R_RISCV_SUB32 w 0x0
14+
# CHECK-NEXT: 0x14 R_RISCV_ADD32 w1 0x0
15+
# CHECK-NEXT: 0x14 R_RISCV_SUB32 w 0x0
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# CHECK-NEXT: 0x18 R_RISCV_ADD32 .L.str 0x0
17+
# CHECK-NEXT: 0x18 R_RISCV_SUB32 w 0x0
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# CHECK-NEXT: }
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# CHECK-NEXT: Section ({{.*}}) .rela.alloc_x {
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# CHECK-NEXT: 0x0 R_RISCV_ADD64 y 0x0
@@ -34,8 +40,13 @@
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.endif
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.section .alloc_w,"aw",@progbits; w:
37-
.quad extern-w
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.quad extern-w # extern is undefined
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.quad w-extern
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.long x-w # A is later defined in another section
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.long w1-w # A is later defined in the same section
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.long .L.str-w # A is temporary
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w1:
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.section .alloc_x,"aw",@progbits; x:
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.quad y-x
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.section .alloc_y,"aw",@progbits; y:
@@ -56,6 +67,17 @@
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.section .nonalloc_y; ny:
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.quad nx-ny
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## -gdwarf-aranges generated assembly expects no relocation.
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## Otherwise, a .Lsec_end0 symbol (defined at the end of .rodata.str1.1)
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## will be rejected by linkers.
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.section .rodata.str1.1,"aMS",@progbits,1
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.L.str:
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.asciz "hello"
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.section .rodata.str1.1,"aMS",@progbits,1
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.Lsec_end0:
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.section .debug_aranges,"",@progbits
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.quad .Lsec_end0-.L.str
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## .apple_names/.apple_types are fixed-size and do not need fixups.
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## llvm-dwarfdump --apple-names does not process R_RISCV_{ADD,SUB}32 in them.
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## See llvm/test/DebugInfo/Generic/accel-table-hash-collisions.ll

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