Skip to content

Commit c6595ac

Browse files
MacDueMacDue
committed
Split COND_SMSTART/SMSTOP from SMSTART/SMSTOP
1 parent b74b658 commit c6595ac

File tree

4 files changed

+37
-32
lines changed

4 files changed

+37
-32
lines changed

‎llvm/docs/AArch64SME.rst

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -213,12 +213,14 @@ Instruction Selection Nodes
213213

214214
.. code-block:: none
215215
216-
AArch64ISD::SMSTART Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
217-
AArch64ISD::SMSTOP Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
218-
219-
The ``SMSTART/SMSTOP`` nodes take ``CurrentState`` and ``ExpectedState`` operand for
220-
the case of a conditional SMSTART/SMSTOP. The instruction will only be executed
221-
if CurrentState != ExpectedState.
216+
AArch64ISD::SMSTART Chain, [SM|ZA|Both][, RegMask]
217+
AArch64ISD::SMSTOP Chain, [SM|ZA|Both][, RegMask]
218+
AArch64ISD::COND_SMSTART Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
219+
AArch64ISD::COND_SMSTOP Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
220+
221+
The ``COND_SMSTART/COND_SMSTOP`` nodes additionally take ``CurrentState`` and
222+
``ExpectedState``, in this case the instruction will only be executed if
223+
``CurrentState != ExpectedState``.
222224

223225
When ``CurrentState`` and ``ExpectedState`` can be evaluated at compile-time
224226
(i.e. they are both constants) then an unconditional ``smstart/smstop``

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5707,14 +5707,12 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_VOID(SDValue Op,
57075707
return DAG.getNode(
57085708
AArch64ISD::SMSTART, DL, DAG.getVTList(MVT::Other, MVT::Glue),
57095709
Op->getOperand(0), // Chain
5710-
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
5711-
DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
5710+
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
57125711
case Intrinsic::aarch64_sme_za_disable:
57135712
return DAG.getNode(
57145713
AArch64ISD::SMSTOP, DL, DAG.getVTList(MVT::Other, MVT::Glue),
57155714
Op->getOperand(0), // Chain
5716-
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
5717-
DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
5715+
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
57185716
}
57195717
}
57205718

@@ -8587,18 +8585,22 @@ SDValue AArch64TargetLowering::changeStreamingMode(SelectionDAG &DAG, SDLoc DL,
85878585
SDValue RegMask = DAG.getRegisterMask(TRI->getSMStartStopCallPreservedMask());
85888586
SDValue MSROp =
85898587
DAG.getTargetConstant((int32_t)AArch64SVCR::SVCRSM, DL, MVT::i32);
8590-
SDValue ConditionOp = DAG.getTargetConstant(Condition, DL, MVT::i64);
8591-
SmallVector<SDValue> Ops = {Chain, MSROp, ConditionOp};
8588+
SmallVector<SDValue> Ops = {Chain, MSROp};
8589+
unsigned Opcode;
85928590
if (Condition != AArch64SME::Always) {
8591+
SDValue ConditionOp = DAG.getTargetConstant(Condition, DL, MVT::i64);
8592+
Opcode = Enable ? AArch64ISD::COND_SMSTART : AArch64ISD::COND_SMSTOP;
85938593
assert(PStateSM && "PStateSM should be defined");
8594+
Ops.push_back(ConditionOp);
85948595
Ops.push_back(PStateSM);
8596+
} else {
8597+
Opcode = Enable ? AArch64ISD::SMSTART : AArch64ISD::SMSTOP;
85958598
}
85968599
Ops.push_back(RegMask);
85978600

85988601
if (InGlue)
85998602
Ops.push_back(InGlue);
86008603

8601-
unsigned Opcode = Enable ? AArch64ISD::SMSTART : AArch64ISD::SMSTOP;
86028604
return DAG.getNode(Opcode, DL, DAG.getVTList(MVT::Other, MVT::Glue), Ops);
86038605
}
86048606

@@ -8864,8 +8866,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
88648866
if (DisableZA)
88658867
Chain = DAG.getNode(
88668868
AArch64ISD::SMSTOP, DL, DAG.getVTList(MVT::Other, MVT::Glue), Chain,
8867-
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
8868-
DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
8869+
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
88698870

88708871
// Adjust the stack pointer for the new arguments...
88718872
// These operations are automatically eliminated by the prolog/epilog pass
@@ -9343,8 +9344,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
93439344
// Unconditionally resume ZA.
93449345
Result = DAG.getNode(
93459346
AArch64ISD::SMSTART, DL, DAG.getVTList(MVT::Other, MVT::Glue), Result,
9346-
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32),
9347-
DAG.getConstant(AArch64SME::Always, DL, MVT::i64));
9347+
DAG.getTargetConstant((int32_t)(AArch64SVCR::SVCRZA), DL, MVT::i32));
93489348

93499349
if (ShouldPreserveZT0)
93509350
Result =

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Lines changed: 18 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,20 @@
1010
//
1111
//===----------------------------------------------------------------------===//
1212

13-
def AArch64_smstart : SDNode<"AArch64ISD::SMSTART", SDTypeProfile<0, 2,
14-
[SDTCisInt<0>, SDTCisInt<0>]>,
13+
def AArch64_smstart : SDNode<"AArch64ISD::SMSTART", SDTypeProfile<0, 1,
14+
[SDTCisInt<0>]>,
1515
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
1616
SDNPOptInGlue, SDNPOutGlue]>;
17-
def AArch64_smstop : SDNode<"AArch64ISD::SMSTOP", SDTypeProfile<0, 2,
18-
[SDTCisInt<0>, SDTCisInt<0>]>,
17+
def AArch64_smstop : SDNode<"AArch64ISD::SMSTOP", SDTypeProfile<0, 1,
18+
[SDTCisInt<0>]>,
19+
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
20+
SDNPOptInGlue, SDNPOutGlue]>;
21+
def AArch64_cond_smstart : SDNode<"AArch64ISD::COND_SMSTART", SDTypeProfile<0, 3,
22+
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>,
23+
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
24+
SDNPOptInGlue, SDNPOutGlue]>;
25+
def AArch64_cond_smstop : SDNode<"AArch64ISD::COND_SMSTOP", SDTypeProfile<0, 3,
26+
[SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>,
1927
[SDNPHasChain, SDNPSideEffect, SDNPVariadic,
2028
SDNPOptInGlue, SDNPOutGlue]>;
2129
def AArch64_restore_za : SDNode<"AArch64ISD::RESTORE_ZA", SDTypeProfile<0, 3,
@@ -306,15 +314,15 @@ def MSRpstatePseudo :
306314
let Defs = [VG];
307315
}
308316

309-
def : Pat<(AArch64_smstart (i32 svcr_op:$pstate), (i64 timm0_31:$condition)),
310-
(MSRpstatePseudo svcr_op:$pstate, 0b1, timm0_31:$condition)>;
311-
def : Pat<(AArch64_smstop (i32 svcr_op:$pstate), (i64 timm0_31:$condition)),
312-
(MSRpstatePseudo svcr_op:$pstate, 0b0, timm0_31:$condition)>;
317+
def : Pat<(AArch64_cond_smstart (i32 svcr_op:$pstate), (i64 timm0_31:$condition), (i64 GPR64:$pstatesm)),
318+
(MSRpstatePseudo svcr_op:$pstate, 0b1, timm0_31:$condition, GPR64:$pstatesm)>;
319+
def : Pat<(AArch64_cond_smstop (i32 svcr_op:$pstate), (i64 timm0_31:$condition), (i64 GPR64:$pstatesm)),
320+
(MSRpstatePseudo svcr_op:$pstate, 0b0, timm0_31:$condition, GPR64:$pstatesm)>;
313321

314322
// Unconditional start/stop
315-
def : Pat<(AArch64_smstart (i32 svcr_op:$pstate), (i64 /*AArch64SME::Always*/0)),
323+
def : Pat<(AArch64_smstart (i32 svcr_op:$pstate)),
316324
(MSRpstatesvcrImm1 svcr_op:$pstate, 0b1)>;
317-
def : Pat<(AArch64_smstop (i32 svcr_op:$pstate), (i64 /*AArch64SME::Always*/0)),
325+
def : Pat<(AArch64_smstop (i32 svcr_op:$pstate)),
318326
(MSRpstatesvcrImm1 svcr_op:$pstate, 0b0)>;
319327

320328

‎llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -36,11 +36,6 @@ void AArch64SelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
3636
switch (N->getOpcode()) {
3737
default:
3838
return SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
39-
case AArch64ISD::SMSTART:
40-
case AArch64ISD::SMSTOP:
41-
// FIXME: These can't be verified by SelectionDAGGenTargetInfo as the
42-
// variadic "PStateSM" operand is not a Register or RegisterMask.
43-
return;
4439
case AArch64ISD::SADDWT:
4540
case AArch64ISD::SADDWB:
4641
case AArch64ISD::UADDWT:

0 commit comments

Comments
 (0)