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[InstCombine] recognize missed i128 split optimization (#129363)
This pr fixes #126056, recognising a split i128 extension optimization. Proof for working optimization: ```llvm define i128 @src(i32 noundef %x) { entry: %coerce.sroa.0.0.extract.trunc = sext i32 %x to i64 %0 = ashr i32 %x, 31 %coerce.sroa.2.0.extract.trunc = sext i32 %0 to i64 %x.sroa.2.0.insert.ext.i = zext i64 %coerce.sroa.2.0.extract.trunc to i128 %x.sroa.2.0.insert.shift.i = shl nuw i128 %x.sroa.2.0.insert.ext.i, 64 %x.sroa.0.0.insert.ext.i = zext i64 %coerce.sroa.0.0.extract.trunc to i128 %x.sroa.0.0.insert.insert.i = or disjoint i128 %x.sroa.2.0.insert.shift.i, %x.sroa.0.0.insert.ext.i ret i128 %x.sroa.0.0.insert.insert.i } define i128 @tgt(i32 noundef %x) { %x.sroa.0.0.insert.insert.i = sext i32 %x to i128 ret i128 %x.sroa.0.0.insert.insert.i } ```
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‎llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

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Original file line numberDiff line numberDiff line change
@@ -3119,6 +3119,17 @@ static Value *matchOrConcat(Instruction &Or, InstCombiner::BuilderTy &Builder) {
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match(UpperSrc, m_BitReverse(m_Value(UpperBRev))))
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return ConcatIntrinsicCalls(Intrinsic::bitreverse, UpperBRev, LowerBRev);
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// iX ext split: extending or(zext(x),shl(zext(y),bw/2) pattern
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// to consume sext/ashr: or(zext(sext(x)),shl(zext(sext(ashr(x))),bw/2)
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Value *X;
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if (match(LowerSrc, m_SExt(m_Value(X))) &&
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match(UpperSrc,
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m_SExt(m_AShr(
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m_Specific(X),
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m_SpecificInt(X->getType()->getScalarSizeInBits() - 1))))) {
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return Builder.CreateSExt(X, Ty);
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}
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return nullptr;
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}
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‎llvm/test/Transforms/InstCombine/iX-ext-split.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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; PR129363
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; ext split from i32 to i128
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define i128 @i128_ext_split(i32 noundef %x) {
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; CHECK-LABEL: define i128 @i128_ext_split(
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; CHECK-SAME: i32 noundef [[X:%.*]]) {
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; CHECK-NEXT: [[XX:%.*]] = sext i32 [[X]] to i128
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; CHECK-NEXT: ret i128 [[XX]]
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;
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%LowerSrc = sext i32 %x to i64
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%sign = ashr i32 %x, 31
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%UpperSrc = sext i32 %sign to i64
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%widen = zext i64 %UpperSrc to i128
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%hi = shl nuw i128 %widen, 64
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%lo = zext i64 %LowerSrc to i128
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%res = or disjoint i128 %hi, %lo
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ret i128 %res
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}
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; ext split from i32 to i128
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define void @i128_ext_split_store(i32 %x, ptr %out) {
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; CHECK-LABEL: define void @i128_ext_split_store(
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; CHECK-SAME: i32 [[X:%.*]], ptr [[OUT:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[RES:%.*]] = sext i32 [[X]] to i128
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; CHECK-NEXT: store i128 [[RES]], ptr [[OUT]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%LowerSrc = sext i32 %x to i64
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%lo = zext i64 %LowerSrc to i128
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%sign = ashr i32 %x, 31
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%UpperSrc = sext i32 %sign to i64
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%widen = zext i64 %UpperSrc to i128
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%hi = shl nuw i128 %widen, 64
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%res = or disjoint i128 %hi, %lo
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store i128 %res, ptr %out, align 16
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ret void
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}
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; ext split from i16 to i64
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define void @i64_ext_split_store(i16 %x, ptr %out) {
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; CHECK-LABEL: define void @i64_ext_split_store(
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; CHECK-SAME: i16 [[X:%.*]], ptr [[OUT:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[RES:%.*]] = sext i16 [[X]] to i64
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; CHECK-NEXT: store i64 [[RES]], ptr [[OUT]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%LowerSrc = sext i16 %x to i32
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%lo = zext i32 %LowerSrc to i64
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%sign = ashr i16 %x, 15
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%UpperSrc = sext i16 %sign to i32
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%widen = zext i32 %UpperSrc to i64
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%hi = shl nuw i64 %widen, 32
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%res = or disjoint i64 %hi, %lo
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store i64 %res, ptr %out, align 16
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ret void
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}
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; ext split from i16 to i128
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define void @i128_ext_split_store_i16(i16 %x, ptr %out) {
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; CHECK-LABEL: define void @i128_ext_split_store_i16(
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; CHECK-SAME: i16 [[X:%.*]], ptr [[OUT:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[RES:%.*]] = sext i16 [[X]] to i128
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; CHECK-NEXT: store i128 [[RES]], ptr [[OUT]], align 16
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; CHECK-NEXT: ret void
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;
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entry:
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%LowerSrc = sext i16 %x to i64
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%lo = zext i64 %LowerSrc to i128
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%sign = ashr i16 %x, 15
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%UpperSrc = sext i16 %sign to i64
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%widen = zext i64 %UpperSrc to i128
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%hi = shl nuw i128 %widen, 64
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%res = or disjoint i128 %hi, %lo
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store i128 %res, ptr %out, align 16
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ret void
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}
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; negative test - wrong constant value
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define i128 @i128_ext_split_neg1(i32 %x) {
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; CHECK-LABEL: define i128 @i128_ext_split_neg1(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[LOWERSRC:%.*]] = sext i32 [[X]] to i64
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; CHECK-NEXT: [[LO:%.*]] = zext i64 [[LOWERSRC]] to i128
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; CHECK-NEXT: [[SIGN:%.*]] = ashr i32 [[X]], 31
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; CHECK-NEXT: [[UPPERSRC:%.*]] = sext i32 [[SIGN]] to i64
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; CHECK-NEXT: [[WIDEN:%.*]] = zext i64 [[UPPERSRC]] to i128
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; CHECK-NEXT: [[HI:%.*]] = shl nuw i128 [[WIDEN]], 65
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; CHECK-NEXT: [[RES:%.*]] = or disjoint i128 [[HI]], [[LO]]
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; CHECK-NEXT: ret i128 [[RES]]
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;
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entry:
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%LowerSrc = sext i32 %x to i64
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%lo = zext i64 %LowerSrc to i128
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%sign = ashr i32 %x, 31
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%UpperSrc = sext i32 %sign to i64
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%widen = zext i64 %UpperSrc to i128
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%hi = shl nuw i128 %widen, 65
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%res = or disjoint i128 %hi, %lo
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ret i128 %res
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}
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; negative test - wrong shift value
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define i128 @i128_ext_split_neg2(i32 %x) {
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; CHECK-LABEL: define i128 @i128_ext_split_neg2(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[LOWERSRC:%.*]] = sext i32 [[X]] to i64
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; CHECK-NEXT: [[LO:%.*]] = zext i64 [[LOWERSRC]] to i128
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; CHECK-NEXT: [[SIGN:%.*]] = ashr i32 [[X]], 3
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; CHECK-NEXT: [[UPPERSRC:%.*]] = sext i32 [[SIGN]] to i64
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; CHECK-NEXT: [[WIDEN:%.*]] = zext i64 [[UPPERSRC]] to i128
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; CHECK-NEXT: [[HI:%.*]] = shl nuw i128 [[WIDEN]], 64
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; CHECK-NEXT: [[RES:%.*]] = or disjoint i128 [[HI]], [[LO]]
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; CHECK-NEXT: ret i128 [[RES]]
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;
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entry:
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%LowerSrc = sext i32 %x to i64
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%lo = zext i64 %LowerSrc to i128
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%sign = ashr i32 %x, 3
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%UpperSrc = sext i32 %sign to i64
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%widen = zext i64 %UpperSrc to i128
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%hi = shl nuw i128 %widen, 64
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%res = or disjoint i128 %hi, %lo
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ret i128 %res
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}
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; negative test - wrong ext instruction
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define i128 @i128_ext_split_neg3(i32 %x) {
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; CHECK-LABEL: define i128 @i128_ext_split_neg3(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[LO:%.*]] = zext i32 [[X]] to i128
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; CHECK-NEXT: [[SIGN:%.*]] = ashr i32 [[X]], 31
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; CHECK-NEXT: [[UPPERSRC:%.*]] = sext i32 [[SIGN]] to i64
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; CHECK-NEXT: [[WIDEN:%.*]] = zext i64 [[UPPERSRC]] to i128
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; CHECK-NEXT: [[HI:%.*]] = shl nuw i128 [[WIDEN]], 64
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; CHECK-NEXT: [[RES:%.*]] = or disjoint i128 [[HI]], [[LO]]
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; CHECK-NEXT: ret i128 [[RES]]
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;
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entry:
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%LowerSrc = zext i32 %x to i64
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%lo = zext i64 %LowerSrc to i128
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%sign = ashr i32 %x, 31
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%UpperSrc = sext i32 %sign to i64
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%widen = zext i64 %UpperSrc to i128
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%hi = shl nuw i128 %widen, 64
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%res = or disjoint i128 %hi, %lo
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ret i128 %res
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}
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; negative test - wrong shift
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define i128 @i128_ext_split_neg4(i32 %x) {
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; CHECK-LABEL: define i128 @i128_ext_split_neg4(
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; CHECK-SAME: i32 [[X:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: [[LOWERSRC:%.*]] = sext i32 [[X]] to i64
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; CHECK-NEXT: [[LO:%.*]] = zext i64 [[LOWERSRC]] to i128
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; CHECK-NEXT: [[SIGN:%.*]] = lshr i32 [[X]], 31
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; CHECK-NEXT: [[WIDEN:%.*]] = zext nneg i32 [[SIGN]] to i128
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; CHECK-NEXT: [[HI:%.*]] = shl nuw nsw i128 [[WIDEN]], 64
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; CHECK-NEXT: [[RES:%.*]] = or disjoint i128 [[HI]], [[LO]]
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; CHECK-NEXT: ret i128 [[RES]]
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;
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entry:
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%LowerSrc = sext i32 %x to i64
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%lo = zext i64 %LowerSrc to i128
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%sign = lshr i32 %x, 31
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%UpperSrc = sext i32 %sign to i64
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%widen = zext i64 %UpperSrc to i128
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%hi = shl nuw i128 %widen, 64
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%res = or disjoint i128 %hi, %lo
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ret i128 %res
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}

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