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[RISCV] Add sext_inreg patterns for XAndesPerf nds.bfos instruction (#139714)
Add the patterns sign_extend_inreg i1/i8/i16.
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5 files changed

+298
-6
lines changed

5 files changed

+298
-6
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -310,13 +310,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
310310
setOperationAction(ISD::VASTART, MVT::Other, Custom);
311311
setOperationAction({ISD::VAARG, ISD::VACOPY, ISD::VAEND}, MVT::Other, Expand);
312312

313-
if (!Subtarget.hasVendorXTHeadBb() && !Subtarget.hasVendorXqcibm())
313+
if (!Subtarget.hasVendorXTHeadBb() && !Subtarget.hasVendorXqcibm() &&
314+
!Subtarget.hasVendorXAndesPerf())
314315
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
315316

316317
setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
317318

318319
if (!Subtarget.hasStdExtZbb() && !Subtarget.hasVendorXTHeadBb() &&
319-
!Subtarget.hasVendorXqcibm() &&
320+
!Subtarget.hasVendorXqcibm() && !Subtarget.hasVendorXAndesPerf() &&
320321
!(Subtarget.hasVendorXCValu() && !Subtarget.is64Bit()))
321322
setOperationAction(ISD::SIGN_EXTEND_INREG, {MVT::i8, MVT::i16}, Expand);
322323

‎llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -466,6 +466,10 @@ def NDS_VD4DOTSU_VV : NDSRVInstVD4DOT<0b000101, "nds.vd4dotsu">;
466466

467467
let Predicates = [HasVendorXAndesPerf] in {
468468

469+
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (NDS_BFOS GPR:$rs1, 15, 0)>;
470+
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (NDS_BFOS GPR:$rs1, 7, 0)>;
471+
def : Pat<(sext_inreg (XLenVT GPR:$rs1), i1), (NDS_BFOS GPR:$rs1, 0, 0)>;
472+
469473
defm : ShxAddPat<1, NDS_LEA_H>;
470474
defm : ShxAddPat<2, NDS_LEA_W>;
471475
defm : ShxAddPat<3, NDS_LEA_D>;

‎llvm/test/CodeGen/RISCV/rv32xandesperf.ll

Lines changed: 152 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,152 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -O0 -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s
4+
5+
define i32 @sexti1_i32(i32 %a) {
6+
; CHECK-LABEL: sexti1_i32:
7+
; CHECK: # %bb.0:
8+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
9+
; CHECK-NEXT: ret
10+
%shl = shl i32 %a, 31
11+
%shr = ashr exact i32 %shl, 31
12+
ret i32 %shr
13+
}
14+
15+
define i32 @sexti1_i32_2(i1 %a) {
16+
; CHECK-LABEL: sexti1_i32_2:
17+
; CHECK: # %bb.0:
18+
; CHECK-NEXT: # kill: def $x11 killed $x10
19+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
20+
; CHECK-NEXT: ret
21+
%1 = sext i1 %a to i32
22+
ret i32 %1
23+
}
24+
25+
define i32 @sexti8_i32(i32 %a) {
26+
; CHECK-LABEL: sexti8_i32:
27+
; CHECK: # %bb.0:
28+
; CHECK-NEXT: nds.bfos a0, a0, 7, 0
29+
; CHECK-NEXT: ret
30+
%shl = shl i32 %a, 24
31+
%shr = ashr exact i32 %shl, 24
32+
ret i32 %shr
33+
}
34+
35+
define i32 @sexti8_i32_2(i8 %a) {
36+
; CHECK-LABEL: sexti8_i32_2:
37+
; CHECK: # %bb.0:
38+
; CHECK-NEXT: # kill: def $x11 killed $x10
39+
; CHECK-NEXT: nds.bfos a0, a0, 7, 0
40+
; CHECK-NEXT: ret
41+
%1 = sext i8 %a to i32
42+
ret i32 %1
43+
}
44+
45+
define i32 @sexti16_i32(i32 %a) {
46+
; CHECK-LABEL: sexti16_i32:
47+
; CHECK: # %bb.0:
48+
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
49+
; CHECK-NEXT: ret
50+
%shl = shl i32 %a, 16
51+
%shr = ashr exact i32 %shl, 16
52+
ret i32 %shr
53+
}
54+
55+
define i32 @sexti16_i32_2(i16 %a) {
56+
; CHECK-LABEL: sexti16_i32_2:
57+
; CHECK: # %bb.0:
58+
; CHECK-NEXT: # kill: def $x11 killed $x10
59+
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
60+
; CHECK-NEXT: ret
61+
%1 = sext i16 %a to i32
62+
ret i32 %1
63+
}
64+
65+
define i64 @sexti1_i64(i64 %a) {
66+
; CHECK-LABEL: sexti1_i64:
67+
; CHECK: # %bb.0:
68+
; CHECK-NEXT: # kill: def $x11 killed $x10
69+
; CHECK-NEXT: nds.bfos a1, a0, 0, 0
70+
; CHECK-NEXT: mv a0, a1
71+
; CHECK-NEXT: ret
72+
%shl = shl i64 %a, 63
73+
%shr = ashr exact i64 %shl, 63
74+
ret i64 %shr
75+
}
76+
77+
define i64 @sexti1_i64_2(i1 %a) {
78+
; CHECK-LABEL: sexti1_i64_2:
79+
; CHECK: # %bb.0:
80+
; CHECK-NEXT: # kill: def $x11 killed $x10
81+
; CHECK-NEXT: nds.bfos a1, a0, 0, 0
82+
; CHECK-NEXT: mv a0, a1
83+
; CHECK-NEXT: ret
84+
%1 = sext i1 %a to i64
85+
ret i64 %1
86+
}
87+
88+
define i64 @sexti8_i64(i64 %a) {
89+
; CHECK-LABEL: sexti8_i64:
90+
; CHECK: # %bb.0:
91+
; CHECK-NEXT: # kill: def $x11 killed $x10
92+
; CHECK-NEXT: nds.bfos a0, a0, 7, 0
93+
; CHECK-NEXT: srai a1, a0, 31
94+
; CHECK-NEXT: ret
95+
%shl = shl i64 %a, 56
96+
%shr = ashr exact i64 %shl, 56
97+
ret i64 %shr
98+
}
99+
100+
define i64 @sexti8_i64_2(i8 %a) {
101+
; CHECK-LABEL: sexti8_i64_2:
102+
; CHECK: # %bb.0:
103+
; CHECK-NEXT: # kill: def $x11 killed $x10
104+
; CHECK-NEXT: nds.bfos a0, a0, 7, 0
105+
; CHECK-NEXT: srai a1, a0, 31
106+
; CHECK-NEXT: ret
107+
%1 = sext i8 %a to i64
108+
ret i64 %1
109+
}
110+
111+
define i64 @sexti16_i64(i64 %a) {
112+
; CHECK-LABEL: sexti16_i64:
113+
; CHECK: # %bb.0:
114+
; CHECK-NEXT: # kill: def $x11 killed $x10
115+
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
116+
; CHECK-NEXT: srai a1, a0, 31
117+
; CHECK-NEXT: ret
118+
%shl = shl i64 %a, 48
119+
%shr = ashr exact i64 %shl, 48
120+
ret i64 %shr
121+
}
122+
123+
define i64 @sexti16_i64_2(i16 %a) {
124+
; CHECK-LABEL: sexti16_i64_2:
125+
; CHECK: # %bb.0:
126+
; CHECK-NEXT: # kill: def $x11 killed $x10
127+
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
128+
; CHECK-NEXT: srai a1, a0, 31
129+
; CHECK-NEXT: ret
130+
%1 = sext i16 %a to i64
131+
ret i64 %1
132+
}
133+
134+
define i64 @sexti32_i64(i64 %a) {
135+
; CHECK-LABEL: sexti32_i64:
136+
; CHECK: # %bb.0:
137+
; CHECK-NEXT: # kill: def $x11 killed $x10
138+
; CHECK-NEXT: srai a1, a0, 31
139+
; CHECK-NEXT: ret
140+
%shl = shl i64 %a, 32
141+
%shr = ashr exact i64 %shl, 32
142+
ret i64 %shr
143+
}
144+
145+
define i64 @sexti32_i64_2(i32 %a) {
146+
; CHECK-LABEL: sexti32_i64_2:
147+
; CHECK: # %bb.0:
148+
; CHECK-NEXT: srai a1, a0, 31
149+
; CHECK-NEXT: ret
150+
%1 = sext i32 %a to i64
151+
ret i64 %1
152+
}

‎llvm/test/CodeGen/RISCV/rv64xandesperf.ll

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,135 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=riscv64 -mattr=+xandesperf -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s
4+
5+
define signext i32 @sexti1_i32(i32 signext %a) {
6+
; CHECK-LABEL: sexti1_i32:
7+
; CHECK: # %bb.0:
8+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
9+
; CHECK-NEXT: ret
10+
%shl = shl i32 %a, 31
11+
%shr = ashr exact i32 %shl, 31
12+
ret i32 %shr
13+
}
14+
15+
define signext i32 @sexti1_i32_2(i1 %a) {
16+
; CHECK-LABEL: sexti1_i32_2:
17+
; CHECK: # %bb.0:
18+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
19+
; CHECK-NEXT: ret
20+
%1 = sext i1 %a to i32
21+
ret i32 %1
22+
}
23+
24+
define signext i32 @sexti8_i32(i32 signext %a) {
25+
; CHECK-LABEL: sexti8_i32:
26+
; CHECK: # %bb.0:
27+
; CHECK-NEXT: nds.bfos a0, a0, 7, 0
28+
; CHECK-NEXT: ret
29+
%shl = shl i32 %a, 24
30+
%shr = ashr exact i32 %shl, 24
31+
ret i32 %shr
32+
}
33+
34+
define signext i32 @sexti8_i32_2(i8 %a) {
35+
; CHECK-LABEL: sexti8_i32_2:
36+
; CHECK: # %bb.0:
37+
; CHECK-NEXT: nds.bfos a0, a0, 7, 0
38+
; CHECK-NEXT: ret
39+
%1 = sext i8 %a to i32
40+
ret i32 %1
41+
}
42+
43+
define signext i32 @sexti16_i32(i32 signext %a) {
44+
; CHECK-LABEL: sexti16_i32:
45+
; CHECK: # %bb.0:
46+
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
47+
; CHECK-NEXT: ret
48+
%shl = shl i32 %a, 16
49+
%shr = ashr exact i32 %shl, 16
50+
ret i32 %shr
51+
}
52+
53+
define signext i32 @sexti16_i32_2(i16 %a) {
54+
; CHECK-LABEL: sexti16_i32_2:
55+
; CHECK: # %bb.0:
56+
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
57+
; CHECK-NEXT: ret
58+
%1 = sext i16 %a to i32
59+
ret i32 %1
60+
}
61+
62+
define i64 @sexti1_i64(i64 %a) {
63+
; CHECK-LABEL: sexti1_i64:
64+
; CHECK: # %bb.0:
65+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
66+
; CHECK-NEXT: ret
67+
%shl = shl i64 %a, 63
68+
%shr = ashr exact i64 %shl, 63
69+
ret i64 %shr
70+
}
71+
72+
define i64 @sexti1_i64_2(i1 %a) {
73+
; CHECK-LABEL: sexti1_i64_2:
74+
; CHECK: # %bb.0:
75+
; CHECK-NEXT: nds.bfos a0, a0, 0, 0
76+
; CHECK-NEXT: ret
77+
%1 = sext i1 %a to i64
78+
ret i64 %1
79+
}
80+
81+
define i64 @sexti8_i64(i64 %a) {
82+
; CHECK-LABEL: sexti8_i64:
83+
; CHECK: # %bb.0:
84+
; CHECK-NEXT: nds.bfos a0, a0, 7, 0
85+
; CHECK-NEXT: ret
86+
%shl = shl i64 %a, 56
87+
%shr = ashr exact i64 %shl, 56
88+
ret i64 %shr
89+
}
90+
91+
define i64 @sexti8_i64_2(i8 %a) {
92+
; CHECK-LABEL: sexti8_i64_2:
93+
; CHECK: # %bb.0:
94+
; CHECK-NEXT: nds.bfos a0, a0, 7, 0
95+
; CHECK-NEXT: ret
96+
%1 = sext i8 %a to i64
97+
ret i64 %1
98+
}
99+
100+
define i64 @sexti16_i64(i64 %a) {
101+
; CHECK-LABEL: sexti16_i64:
102+
; CHECK: # %bb.0:
103+
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
104+
; CHECK-NEXT: ret
105+
%shl = shl i64 %a, 48
106+
%shr = ashr exact i64 %shl, 48
107+
ret i64 %shr
108+
}
109+
110+
define i64 @sexti16_i64_2(i16 %a) {
111+
; CHECK-LABEL: sexti16_i64_2:
112+
; CHECK: # %bb.0:
113+
; CHECK-NEXT: nds.bfos a0, a0, 15, 0
114+
; CHECK-NEXT: ret
115+
%1 = sext i16 %a to i64
116+
ret i64 %1
117+
}
118+
119+
define i64 @sexti32_i64(i64 %a) {
120+
; CHECK-LABEL: sexti32_i64:
121+
; CHECK: # %bb.0:
122+
; CHECK-NEXT: sext.w a0, a0
123+
; CHECK-NEXT: ret
124+
%shl = shl i64 %a, 32
125+
%shr = ashr exact i64 %shl, 32
126+
ret i64 %shr
127+
}
128+
129+
define i64 @sexti32_i64_2(i32 signext %a) {
130+
; CHECK-LABEL: sexti32_i64_2:
131+
; CHECK: # %bb.0:
132+
; CHECK-NEXT: ret
133+
%1 = sext i32 %a to i64
134+
ret i64 %1
135+
}

‎llvm/test/CodeGen/RISCV/rv64zba.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2323,8 +2323,8 @@ define zeroext i32 @sext_ashr_zext_i8(i8 %a) nounwind {
23232323
;
23242324
; RV64XANDESPERF-LABEL: sext_ashr_zext_i8:
23252325
; RV64XANDESPERF: # %bb.0:
2326-
; RV64XANDESPERF-NEXT: slli a0, a0, 56
2327-
; RV64XANDESPERF-NEXT: srai a0, a0, 31
2326+
; RV64XANDESPERF-NEXT: nds.bfos a0, a0, 7, 0
2327+
; RV64XANDESPERF-NEXT: slli a0, a0, 23
23282328
; RV64XANDESPERF-NEXT: srli a0, a0, 32
23292329
; RV64XANDESPERF-NEXT: ret
23302330
%ext = sext i8 %a to i32
@@ -2472,8 +2472,8 @@ define zeroext i32 @sext_ashr_zext_i16(i16 %a) nounwind {
24722472
;
24732473
; RV64XANDESPERF-LABEL: sext_ashr_zext_i16:
24742474
; RV64XANDESPERF: # %bb.0:
2475-
; RV64XANDESPERF-NEXT: slli a0, a0, 48
2476-
; RV64XANDESPERF-NEXT: srai a0, a0, 25
2475+
; RV64XANDESPERF-NEXT: nds.bfos a0, a0, 15, 0
2476+
; RV64XANDESPERF-NEXT: slli a0, a0, 23
24772477
; RV64XANDESPERF-NEXT: srli a0, a0, 32
24782478
; RV64XANDESPERF-NEXT: ret
24792479
%ext = sext i16 %a to i32

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