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[MC][RISCV] Only mark up register part of Rlist
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2 files changed

+68
-19
lines changed

2 files changed

+68
-19
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

Lines changed: 36 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -209,20 +209,33 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
209209
void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
210210
const MCSubtargetInfo &STI, raw_ostream &O) {
211211
unsigned Imm = MI->getOperand(OpNo).getImm();
212-
auto OS = markup(O, Markup::Register);
213-
OS << "{";
212+
O << "{";
214213
switch (Imm) {
215214
case RISCVZC::RLISTENCODE::RA:
216-
OS << (ArchRegNames ? "x1" : "ra");
215+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
217216
break;
218217
case RISCVZC::RLISTENCODE::RA_S0:
219-
OS << (ArchRegNames ? "x1, x8" : "ra, s0");
218+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
219+
O << ", ";
220+
markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
220221
break;
221222
case RISCVZC::RLISTENCODE::RA_S0_S1:
222-
OS << (ArchRegNames ? "x1, x8-x9" : "ra, s0-s1");
223+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
224+
O << ", ";
225+
markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
226+
O << '-';
227+
markup(O, Markup::Register) << (ArchRegNames ? "x9" : "s1");
223228
break;
224229
case RISCVZC::RLISTENCODE::RA_S0_S2:
225-
OS << (ArchRegNames ? "x1, x8-x9, x18" : "ra, s0-s2");
230+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
231+
O << ", ";
232+
markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
233+
O << '-';
234+
markup(O, Markup::Register) << (ArchRegNames ? "x9" : "s2");
235+
if (ArchRegNames) {
236+
O << ", ";
237+
markup(O, Markup::Register) << "x18";
238+
}
226239
break;
227240
case RISCVZC::RLISTENCODE::RA_S0_S3:
228241
case RISCVZC::RLISTENCODE::RA_S0_S4:
@@ -231,16 +244,26 @@ void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
231244
case RISCVZC::RLISTENCODE::RA_S0_S7:
232245
case RISCVZC::RLISTENCODE::RA_S0_S8:
233246
case RISCVZC::RLISTENCODE::RA_S0_S9:
234-
OS << (ArchRegNames ? "x1, x8-x9, x18-" : "ra, s0-")
235-
<< getRegisterName(RISCV::X19 + (Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
236-
break;
237247
case RISCVZC::RLISTENCODE::RA_S0_S11:
238-
OS << (ArchRegNames ? "x1, x8-x9, x18-x27" : "ra, s0-s11");
248+
markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
249+
O << ", ";
250+
markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
251+
O << '-';
252+
if (ArchRegNames) {
253+
markup(O, Markup::Register) << "x9";
254+
O << ", ";
255+
markup(O, Markup::Register) << "x18";
256+
O << '-';
257+
}
258+
markup(O, Markup::Register) << getRegisterName(
259+
RISCV::X19 + (Imm == RISCVZC::RLISTENCODE::RA_S0_S11
260+
? 8
261+
: Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
239262
break;
240263
default:
241264
llvm_unreachable("invalid register list");
242265
}
243-
OS << "}";
266+
O << "}";
244267
}
245268

246269
void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
@@ -258,6 +281,7 @@ void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
258281
if (Opcode == RISCV::CM_PUSH)
259282
Spimm = -Spimm;
260283

284+
// RAII guard for ANSI color escape sequences
261285
auto OS = markup(O, Markup::Immediate);
262286
RISCVZC::printSpimm(Spimm, O);
263287
}
@@ -272,7 +296,7 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
272296
return;
273297
O << ", ";
274298
printRegName(O, MO.getReg());
275-
O << ".t";
299+
markup(O, Markup::Register) << ".t";
276300
}
277301

278302
const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {

‎llvm/test/MC/Disassembler/RISCV/colored.txt

Lines changed: 32 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,48 @@
1-
# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa --cdis %s | FileCheck %s --strict-whitespace --match-full-lines
1+
# UNSUPPORTED: system-windows
2+
# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa,+v --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=CHECK,ASM,ABINAME
3+
# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+experimental-zfa,+v -M numeric --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=CHECK,ASM,ARCHNAME
24

5+
# CHECK: .text
36
# Registers and immediates
47
0x03 0xe0 0x40 0x00
5-
# CHECK: lwu zero, 4(ra)
8+
# ABINAME-NEXT: lwu zero, 4(ra)
9+
# ARCHNAME-NEXT: lwu x0, 4(x1)
610

711
# Branch targets
812
0x63 0x00 0xb5 0x04
9-
# CHECK-NEXT: beq a0, a1, 64
13+
# ABINAME-NEXT: beq a0, a1, 64
14+
# ARCHNAME-NEXT: beq x10, x11, 64
1015

1116
# CSRs
1217
0xf3 0x23 0x10 0xf1
13-
# CHECK-NEXT: csrr t2, mvendorid
18+
# ABINAME-NEXT: csrr t2, mvendorid
19+
# ARCHNAME-NEXT: csrr x7, mvendorid
1420

1521
# FP immediates
1622
0xd3 0x00 0x1f 0xf0
17-
# CHECK-NEXT: fli.s ft1, inf
23+
# ABINAME-NEXT: fli.s ft1, inf
24+
# ARCHNAME-NEXT: fli.s f1, inf
1825
0xd3 0x80 0x1e 0xf0
19-
# CHECK-NEXT: fli.s ft1, 65536.0
26+
# ABINAME-NEXT: fli.s ft1, 65536.0
27+
# ARCHNAME-NEXT: fli.s f1, 65536.0
2028

2129
# Rlist and spimm
30+
0x42 0xbe
31+
# ABINAME-NEXT: cm.popret {ra}, 16
32+
# ARCHNAME-NEXT: cm.popret {x1}, 16
33+
0x5e 0xbe
34+
# ABINAME-NEXT: cm.popret {ra, s0}, 64
35+
# ARCHNAME-NEXT: cm.popret {x1, x8}, 64
2236
0x62 0xbe
23-
# CHECK-NEXT: cm.popret {ra, s0-s1}, 32
37+
# ABINAME-NEXT: cm.popret {ra, s0-s1}, 32
38+
# ARCHNAME-NEXT: cm.popret {x1, x8-x9}, 32
39+
0x76 0xbe
40+
# ABINAME-NEXT: cm.popret {ra, s0-s2}, 48
41+
# ARCHNAME-NEXT: cm.popret {x1, x8-x9, x18}, 48
42+
0xfe 0xbe
43+
# ABINAME-NEXT: cm.popret {ra, s0-s11}, 160
44+
# ARCHNAME-NEXT: cm.popret {x1, x8-x9, x18-x27}, 160
45+
46+
# mask registers
47+
0x57 0x04 0x4a 0x00
48+
# ASM-NEXT: vadd.vv v8, v4, v20, v0.t

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