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Add tablegen patterns
1 parent 1785d27 commit ca33763

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4 files changed

+37
-11
lines changed

4 files changed

+37
-11
lines changed

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -98,8 +98,8 @@ def : GINodeEquiv<G_FPTOSI, fp_to_sint>;
9898
def : GINodeEquiv<G_FPTOUI, fp_to_uint>;
9999
def : GINodeEquiv<G_SITOFP, sint_to_fp>;
100100
def : GINodeEquiv<G_UITOFP, uint_to_fp>;
101-
def : GINodeEquiv<G_FPTOSI_SAT, fp_to_sint_sat>;
102-
def : GINodeEquiv<G_FPTOUI_SAT, fp_to_uint_sat>;
101+
def : GINodeEquiv<G_FPTOSI_SAT, fp_to_sint_sat_gi>;
102+
def : GINodeEquiv<G_FPTOUI_SAT, fp_to_uint_sat_gi>;
103103
def : GINodeEquiv<G_FADD, fadd>;
104104
def : GINodeEquiv<G_FSUB, fsub>;
105105
def : GINodeEquiv<G_FMA, fma>;

llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -564,6 +564,8 @@ def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
564564
def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
565565
def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>;
566566
def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>;
567+
def fp_to_sint_sat_gi : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntOp>;
568+
def fp_to_uint_sat_gi : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntOp>;
567569
def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
568570
def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
569571
def bf16_to_fp : SDNode<"ISD::BF16_TO_FP" , SDTIntToFPOp>;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 33 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4709,7 +4709,7 @@ defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
47094709
defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
47104710

47114711
// AArch64's FCVT instructions saturate when out of range.
4712-
multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
4712+
multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string INST> {
47134713
let Predicates = [HasFullFP16] in {
47144714
def : Pat<(i32 (to_int_sat f16:$Rn, i32)),
47154715
(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
@@ -4725,6 +4725,21 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
47254725
def : Pat<(i64 (to_int_sat f64:$Rn, i64)),
47264726
(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
47274727

4728+
let Predicates = [HasFullFP16] in {
4729+
def : Pat<(i32 (to_int_sat_gi f16:$Rn)),
4730+
(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
4731+
def : Pat<(i64 (to_int_sat_gi f16:$Rn)),
4732+
(!cast<Instruction>(INST # UXHr) f16:$Rn)>;
4733+
}
4734+
def : Pat<(i32 (to_int_sat_gi f32:$Rn)),
4735+
(!cast<Instruction>(INST # UWSr) f32:$Rn)>;
4736+
def : Pat<(i64 (to_int_sat_gi f32:$Rn)),
4737+
(!cast<Instruction>(INST # UXSr) f32:$Rn)>;
4738+
def : Pat<(i32 (to_int_sat_gi f64:$Rn)),
4739+
(!cast<Instruction>(INST # UWDr) f64:$Rn)>;
4740+
def : Pat<(i64 (to_int_sat_gi f64:$Rn)),
4741+
(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
4742+
47284743
let Predicates = [HasFullFP16] in {
47294744
def : Pat<(i32 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i32:$scale), i32)),
47304745
(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
@@ -4739,10 +4754,25 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
47394754
(!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
47404755
def : Pat<(i64 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i64:$scale), i64)),
47414756
(!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
4757+
4758+
let Predicates = [HasFullFP16] in {
4759+
def : Pat<(i32 (to_int_sat_gi (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
4760+
(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
4761+
def : Pat<(i64 (to_int_sat_gi (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
4762+
(!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
4763+
}
4764+
def : Pat<(i32 (to_int_sat_gi (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),
4765+
(!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
4766+
def : Pat<(i64 (to_int_sat_gi (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),
4767+
(!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
4768+
def : Pat<(i32 (to_int_sat_gi (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),
4769+
(!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
4770+
def : Pat<(i64 (to_int_sat_gi (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),
4771+
(!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
47424772
}
47434773

4744-
defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
4745-
defm : FPToIntegerSatPats<fp_to_uint_sat, "FCVTZU">;
4774+
defm : FPToIntegerSatPats<fp_to_sint_sat, fp_to_sint_sat_gi, "FCVTZS">;
4775+
defm : FPToIntegerSatPats<fp_to_uint_sat, fp_to_uint_sat_gi, "FCVTZU">;
47464776

47474777
multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
47484778
let Predicates = [HasFullFP16] in {

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2137,12 +2137,6 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
21372137
}
21382138
return false;
21392139
}
2140-
case TargetOpcode::G_FPTOSI_SAT:
2141-
I.setDesc(TII.get(TargetOpcode::G_FPTOSI));
2142-
return true;
2143-
case TargetOpcode::G_FPTOUI_SAT:
2144-
I.setDesc(TII.get(TargetOpcode::G_FPTOUI));
2145-
return true;
21462140
default:
21472141
return false;
21482142
}

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