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sjoerdmeijersjoerdmeijer
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[LoopInterchange] Precommit tests for scalar dependencies. NFC. (#115900)
We are miscompiling and incorrectly interchanging loops with scalar dependencies that are live-out and conditionally set. This precommits some tests demonstrating this. This is based on the tests in https://reviews.llvm.org/D87879 by `mdchen`.
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‎llvm/test/Transforms/LoopInterchange/gh54176-scalar-deps.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -passes=loop-interchange -S | FileCheck %s
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@f = dso_local local_unnamed_addr global [4 x [9 x i32]] [[9 x i32] [i32 5, i32 3, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0], [9 x i32] zeroinitializer, [9 x i32] zeroinitializer, [9 x i32] zeroinitializer], align 4
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@g = common dso_local local_unnamed_addr global i32 0, align 4
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; int32_t f[3][3];
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; int32_t g;
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;
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; int32_t test1(_Bool cond) {
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; for (int64_t i = 0; i < 3; i++) {
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; for (int64_t j = 0; j < 3; j++) {
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; int32_t val = f[i][j];
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; if (val == 0)
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; if (!cond)
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; g++;
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; else
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; g = 3;
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; if (!cond)
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; g++;
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; }
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; }
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; return g;
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; }
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;
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; FIXME: if there's an output dependency inside the loop and Src doesn't
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; dominate Dst, we should not interchange. Thus, this currently miscompiles.
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;
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define dso_local i32 @test1(i1 %cond) {
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; CHECK-LABEL: define dso_local i32 @test1(
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; CHECK-SAME: i1 [[COND:%.*]]) {
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; CHECK-NEXT: [[FOR_PREHEADER:.*:]]
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; CHECK-NEXT: br label %[[INNERLOOP_PREHEADER:.*]]
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; CHECK: [[OUTERLOOP_PREHEADER:.*]]:
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; CHECK-NEXT: br label %[[OUTERLOOP:.*]]
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; CHECK: [[OUTERLOOP]]:
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; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT21_I:%.*]], %[[FOR_LATCH:.*]] ], [ 0, %[[OUTERLOOP_PREHEADER]] ]
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; CHECK-NEXT: br label %[[INNERLOOP_SPLIT:.*]]
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; CHECK: [[INNERLOOP_PREHEADER]]:
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; CHECK-NEXT: br label %[[INNERLOOP:.*]]
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; CHECK: [[INNERLOOP]]:
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; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[TMP0:%.*]], %[[IF_END_SPLIT:.*]] ], [ 0, %[[INNERLOOP_PREHEADER]] ]
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; CHECK-NEXT: br label %[[OUTERLOOP_PREHEADER]]
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; CHECK: [[INNERLOOP_SPLIT]]:
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; CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [4 x [9 x i32]], ptr @f, i64 0, i64 [[J]], i64 [[I]]
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; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[ARRAYIDX6_I]], align 4
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; CHECK-NEXT: [[TOBOOL_I:%.*]] = icmp eq i32 [[I1]], 0
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; CHECK-NEXT: br i1 [[TOBOOL_I]], label %[[LAND_END:.*]], label %[[LAND_RHS:.*]]
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; CHECK: [[LAND_RHS]]:
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; CHECK-NEXT: store i32 3, ptr @g, align 4
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; CHECK-NEXT: br label %[[LAND_END]]
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; CHECK: [[LAND_END]]:
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; CHECK-NEXT: br i1 [[COND]], label %[[IF_END:.*]], label %[[IF_THEN:.*]]
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; CHECK: [[IF_THEN]]:
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; CHECK-NEXT: [[I2:%.*]] = load i32, ptr @g, align 4
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; CHECK-NEXT: [[INC_I:%.*]] = add i32 [[I2]], 1
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; CHECK-NEXT: store i32 [[INC_I]], ptr @g, align 4
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; CHECK-NEXT: br label %[[IF_END]]
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; CHECK: [[IF_END]]:
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; CHECK-NEXT: [[J_NEXT:%.*]] = add nuw nsw i64 [[J]], 1
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; CHECK-NEXT: [[EXITCOND_I:%.*]] = icmp eq i64 [[J_NEXT]], 3
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; CHECK-NEXT: br label %[[FOR_LATCH]]
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; CHECK: [[IF_END_SPLIT]]:
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; CHECK-NEXT: [[TMP0]] = add nuw nsw i64 [[J]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 3
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; CHECK-NEXT: br i1 [[TMP1]], label %[[EXIT:.*]], label %[[INNERLOOP]]
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; CHECK: [[FOR_LATCH]]:
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; CHECK-NEXT: [[INDVARS_IV_NEXT21_I]] = add nsw i64 [[I]], 1
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; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i64 [[I]], 2
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; CHECK-NEXT: br i1 [[CMP_I]], label %[[OUTERLOOP]], label %[[IF_END_SPLIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[I3:%.*]] = load i32, ptr @g, align 4
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; CHECK-NEXT: ret i32 [[I3]]
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;
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for.preheader:
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br label %outerloop
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outerloop:
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%i = phi i64 [ 0, %for.preheader ], [ %indvars.iv.next21.i, %for.latch ]
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br label %innerloop
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innerloop:
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%j = phi i64 [ 0, %outerloop ], [ %j.next, %if.end ]
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%arrayidx6.i = getelementptr inbounds [4 x [9 x i32]], [4 x [9 x i32]]* @f, i64 0, i64 %j, i64 %i
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%i1 = load i32, i32* %arrayidx6.i, align 4
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%tobool.i = icmp eq i32 %i1, 0
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br i1 %tobool.i, label %land.end, label %land.rhs
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land.rhs:
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store i32 3, i32* @g, align 4
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br label %land.end
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land.end:
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br i1 %cond, label %if.end, label %if.then
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if.then:
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%i2 = load i32, i32* @g, align 4
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%inc.i = add i32 %i2, 1
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store i32 %inc.i, i32* @g, align 4
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br label %if.end
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if.end:
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%j.next = add nuw nsw i64 %j, 1
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%exitcond.i = icmp eq i64 %j.next, 3
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br i1 %exitcond.i, label %for.latch, label %innerloop
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for.latch:
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%indvars.iv.next21.i = add nsw i64 %i, 1
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%cmp.i = icmp slt i64 %i, 2
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br i1 %cmp.i, label %outerloop, label %exit
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exit:
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%i3 = load i32, i32* @g, align 4
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ret i32 %i3
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}
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; int32_t f[3][3];
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; int32_t g;
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;
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; int32_t test2(_Bool cond) {
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; for (int64_t i = 0; i < 3; i++) {
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; for (int64_t j = 0; j < 3; j++) {
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; int32_t val = f[i][j];
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; g = 3;
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; if (val == 0)
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; if (!cond)
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; g++;
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; else
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; if (!cond)
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; g++;
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; }
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; }
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; return g;
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; }
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;
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; FIXME: if there's an output dependency inside the loop and Src doesn't
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; dominate Dst, we should not interchange. Thus, this currently miscompiles.
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;
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define dso_local i32 @test2(i1 %cond) {
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; CHECK-LABEL: define dso_local i32 @test2(
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; CHECK-SAME: i1 [[COND:%.*]]) {
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; CHECK-NEXT: [[FOR_PREHEADER:.*:]]
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; CHECK-NEXT: br label %[[INNERLOOP_PREHEADER:.*]]
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; CHECK: [[OUTERLOOP_PREHEADER:.*]]:
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; CHECK-NEXT: br label %[[OUTERLOOP:.*]]
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; CHECK: [[OUTERLOOP]]:
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; CHECK-NEXT: [[I:%.*]] = phi i64 [ [[INDVARS_IV_NEXT21_I:%.*]], %[[FOR_LATCH:.*]] ], [ 0, %[[OUTERLOOP_PREHEADER]] ]
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; CHECK-NEXT: br label %[[INNERLOOP_SPLIT:.*]]
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; CHECK: [[INNERLOOP_PREHEADER]]:
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; CHECK-NEXT: br label %[[INNERLOOP:.*]]
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; CHECK: [[INNERLOOP]]:
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; CHECK-NEXT: [[J:%.*]] = phi i64 [ [[TMP0:%.*]], %[[IF_END_SPLIT:.*]] ], [ 0, %[[INNERLOOP_PREHEADER]] ]
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; CHECK-NEXT: br label %[[OUTERLOOP_PREHEADER]]
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; CHECK: [[INNERLOOP_SPLIT]]:
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; CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [4 x [9 x i32]], ptr @f, i64 0, i64 [[J]], i64 [[I]]
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; CHECK-NEXT: [[I1:%.*]] = load i32, ptr [[ARRAYIDX6_I]], align 4
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; CHECK-NEXT: [[TOBOOL_I:%.*]] = icmp eq i32 [[I1]], 0
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; CHECK-NEXT: store i32 3, ptr @g, align 4
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; CHECK-NEXT: br i1 [[TOBOOL_I]], label %[[LAND_END:.*]], label %[[LAND_RHS:.*]]
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; CHECK: [[LAND_RHS]]:
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; CHECK-NEXT: br label %[[LAND_END]]
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; CHECK: [[LAND_END]]:
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; CHECK-NEXT: br i1 [[COND]], label %[[IF_END:.*]], label %[[IF_THEN:.*]]
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; CHECK: [[IF_THEN]]:
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; CHECK-NEXT: [[I2:%.*]] = load i32, ptr @g, align 4
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; CHECK-NEXT: [[INC_I:%.*]] = add i32 [[I2]], 1
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; CHECK-NEXT: store i32 [[INC_I]], ptr @g, align 4
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; CHECK-NEXT: br label %[[IF_END]]
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; CHECK: [[IF_END]]:
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; CHECK-NEXT: [[J_NEXT:%.*]] = add nuw nsw i64 [[J]], 1
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; CHECK-NEXT: [[EXITCOND_I:%.*]] = icmp eq i64 [[J_NEXT]], 3
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; CHECK-NEXT: br label %[[FOR_LATCH]]
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; CHECK: [[IF_END_SPLIT]]:
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; CHECK-NEXT: [[TMP0]] = add nuw nsw i64 [[J]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 3
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; CHECK-NEXT: br i1 [[TMP1]], label %[[EXIT:.*]], label %[[INNERLOOP]]
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; CHECK: [[FOR_LATCH]]:
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; CHECK-NEXT: [[INDVARS_IV_NEXT21_I]] = add nsw i64 [[I]], 1
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; CHECK-NEXT: [[CMP_I:%.*]] = icmp slt i64 [[I]], 2
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; CHECK-NEXT: br i1 [[CMP_I]], label %[[OUTERLOOP]], label %[[IF_END_SPLIT]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[I3:%.*]] = load i32, ptr @g, align 4
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; CHECK-NEXT: ret i32 [[I3]]
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;
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for.preheader:
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br label %outerloop
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outerloop:
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%i = phi i64 [ 0, %for.preheader ], [ %indvars.iv.next21.i, %for.latch ]
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br label %innerloop
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innerloop:
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%j = phi i64 [ 0, %outerloop ], [ %j.next, %if.end ]
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%arrayidx6.i = getelementptr inbounds [4 x [9 x i32]], [4 x [9 x i32]]* @f, i64 0, i64 %j, i64 %i
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%i1 = load i32, i32* %arrayidx6.i, align 4
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%tobool.i = icmp eq i32 %i1, 0
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store i32 3, i32* @g, align 4
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br i1 %tobool.i, label %land.end, label %land.rhs
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land.rhs:
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br label %land.end
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land.end:
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br i1 %cond, label %if.end, label %if.then
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if.then:
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%i2 = load i32, i32* @g, align 4
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%inc.i = add i32 %i2, 1
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store i32 %inc.i, i32* @g, align 4
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br label %if.end
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if.end:
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%j.next = add nuw nsw i64 %j, 1
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%exitcond.i = icmp eq i64 %j.next, 3
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br i1 %exitcond.i, label %for.latch, label %innerloop
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for.latch:
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%indvars.iv.next21.i = add nsw i64 %i, 1
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%cmp.i = icmp slt i64 %i, 2
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br i1 %cmp.i, label %outerloop, label %exit
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exit:
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%i3 = load i32, i32* @g, align 4
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ret i32 %i3
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}

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