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[RISCV] Remove implication of F extension for XTHeadFMemIdx from RISCVFeatures.td.
There is no implies rule in RISCVISAInfo.cpp so this makes them consistent. Soon RISCVFeatures.td will be used to generate RISCVISAInfo.cpp so it won't be possible to mismatch.
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-4
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2 files changed

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-4
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llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1016,8 +1016,7 @@ def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
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def FeatureVendorXTHeadFMemIdx
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: RISCVExtension<"xtheadfmemidx", 1, 0,
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"'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
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[FeatureStdExtF]>;
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"'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;
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def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
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AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),
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"'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;

llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@
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; RV32XSFVFWMACCQQQ: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
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; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
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; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0"
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; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
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; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_xtheadfmemidx1p0"
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; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0"
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; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0"
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; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
@@ -452,7 +452,7 @@
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; RV64XTHEADBS: .attribute 5, "rv64i2p1_xtheadbs1p0"
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; RV64XTHEADCMO: .attribute 5, "rv64i2p1_xtheadcmo1p0"
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; RV64XTHEADCONDMOV: .attribute 5, "rv64i2p1_xtheadcondmov1p0"
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; RV64XTHEADFMEMIDX: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0"
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; RV64XTHEADFMEMIDX: .attribute 5, "rv64i2p1_xtheadfmemidx1p0"
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; RV64XTHEADMAC: .attribute 5, "rv64i2p1_xtheadmac1p0"
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; RV64XTHEADMEMIDX: .attribute 5, "rv64i2p1_xtheadmemidx1p0"
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; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p1_xtheadmempair1p0"

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