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[AArch64] Update and cleanup arm64-vector-imm.ll test. NFC
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‎llvm/test/CodeGen/AArch64/arm64-vector-imm.ll

Lines changed: 89 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -1,134 +1,165 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
23

34
define <8 x i8> @v_orrimm(ptr %A) nounwind {
45
; CHECK-LABEL: v_orrimm:
5-
; CHECK-NOT: mov
6-
; CHECK-NOT: mvn
7-
; CHECK: orr
8-
%tmp1 = load <8 x i8>, ptr %A
9-
%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
10-
ret <8 x i8> %tmp3
6+
; CHECK: // %bb.0:
7+
; CHECK-NEXT: ldr d0, [x0]
8+
; CHECK-NEXT: orr.2s v0, #1, lsl #24
9+
; CHECK-NEXT: ret
10+
%tmp1 = load <8 x i8>, ptr %A
11+
%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
12+
ret <8 x i8> %tmp3
1113
}
1214

1315
define <16 x i8> @v_orrimmQ(ptr %A) nounwind {
14-
; CHECK: v_orrimmQ
15-
; CHECK-NOT: mov
16-
; CHECK-NOT: mvn
17-
; CHECK: orr
18-
%tmp1 = load <16 x i8>, ptr %A
19-
%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
20-
ret <16 x i8> %tmp3
16+
; CHECK-LABEL: v_orrimmQ:
17+
; CHECK: // %bb.0:
18+
; CHECK-NEXT: ldr q0, [x0]
19+
; CHECK-NEXT: orr.4s v0, #1, lsl #24
20+
; CHECK-NEXT: ret
21+
%tmp1 = load <16 x i8>, ptr %A
22+
%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
23+
ret <16 x i8> %tmp3
2124
}
2225

2326
define <8 x i8> @v_bicimm(ptr %A) nounwind {
2427
; CHECK-LABEL: v_bicimm:
25-
; CHECK-NOT: mov
26-
; CHECK-NOT: mvn
27-
; CHECK: bic
28-
%tmp1 = load <8 x i8>, ptr %A
29-
%tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
30-
ret <8 x i8> %tmp3
28+
; CHECK: // %bb.0:
29+
; CHECK-NEXT: ldr d0, [x0]
30+
; CHECK-NEXT: bic.2s v0, #255, lsl #24
31+
; CHECK-NEXT: ret
32+
%tmp1 = load <8 x i8>, ptr %A
33+
%tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
34+
ret <8 x i8> %tmp3
3135
}
3236

3337
define <16 x i8> @v_bicimmQ(ptr %A) nounwind {
3438
; CHECK-LABEL: v_bicimmQ:
35-
; CHECK-NOT: mov
36-
; CHECK-NOT: mvn
37-
; CHECK: bic
38-
%tmp1 = load <16 x i8>, ptr %A
39-
%tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
40-
ret <16 x i8> %tmp3
39+
; CHECK: // %bb.0:
40+
; CHECK-NEXT: ldr q0, [x0]
41+
; CHECK-NEXT: bic.4s v0, #255, lsl #24
42+
; CHECK-NEXT: ret
43+
%tmp1 = load <16 x i8>, ptr %A
44+
%tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
45+
ret <16 x i8> %tmp3
4146
}
4247

4348
define <2 x double> @foo(<2 x double> %bar) nounwind {
44-
; CHECK: foo
45-
; CHECK: fmov.2d v1, #1.0000000
49+
; CHECK-LABEL: foo:
50+
; CHECK: // %bb.0:
51+
; CHECK-NEXT: fmov.2d v1, #1.00000000
52+
; CHECK-NEXT: fadd.2d v0, v0, v1
53+
; CHECK-NEXT: ret
4654
%add = fadd <2 x double> %bar, <double 1.0, double 1.0>
4755
ret <2 x double> %add
4856
}
4957

5058
define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp {
51-
entry:
5259
; CHECK-LABEL: movi_4s_imm_t1:
53-
; CHECK: movi.4s v0, #75
60+
; CHECK: // %bb.0: // %entry
61+
; CHECK-NEXT: movi.4s v0, #75
62+
; CHECK-NEXT: ret
63+
entry:
5464
ret <4 x i32> <i32 75, i32 75, i32 75, i32 75>
5565
}
5666

5767
define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp {
58-
entry:
5968
; CHECK-LABEL: movi_4s_imm_t2:
60-
; CHECK: movi.4s v0, #75, lsl #8
69+
; CHECK: // %bb.0: // %entry
70+
; CHECK-NEXT: movi.4s v0, #75, lsl #8
71+
; CHECK-NEXT: ret
72+
entry:
6173
ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200>
6274
}
6375

6476
define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp {
65-
entry:
6677
; CHECK-LABEL: movi_4s_imm_t3:
67-
; CHECK: movi.4s v0, #75, lsl #16
78+
; CHECK: // %bb.0: // %entry
79+
; CHECK-NEXT: movi.4s v0, #75, lsl #16
80+
; CHECK-NEXT: ret
81+
entry:
6882
ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200>
6983
}
7084

7185
define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp {
72-
entry:
7386
; CHECK-LABEL: movi_4s_imm_t4:
74-
; CHECK: movi.4s v0, #75, lsl #24
87+
; CHECK: // %bb.0: // %entry
88+
; CHECK-NEXT: movi.4s v0, #75, lsl #24
89+
; CHECK-NEXT: ret
90+
entry:
7591
ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
7692
}
7793

7894
define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp {
79-
entry:
8095
; CHECK-LABEL: movi_8h_imm_t5:
81-
; CHECK: movi.8h v0, #75
96+
; CHECK: // %bb.0: // %entry
97+
; CHECK-NEXT: movi.8h v0, #75
98+
; CHECK-NEXT: ret
99+
entry:
82100
ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75>
83101
}
84102

85103
; rdar://11989841
86104
define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp {
87-
entry:
88105
; CHECK-LABEL: movi_8h_imm_t6:
89-
; CHECK: movi.8h v0, #75, lsl #8
106+
; CHECK: // %bb.0: // %entry
107+
; CHECK-NEXT: movi.8h v0, #75, lsl #8
108+
; CHECK-NEXT: ret
109+
entry:
90110
ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200>
91111
}
92112

93113
define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp {
94-
entry:
95114
; CHECK-LABEL: movi_4s_imm_t7:
96-
; CHECK: movi.4s v0, #75, msl #8
97-
ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>
115+
; CHECK: // %bb.0: // %entry
116+
; CHECK-NEXT: movi.4s v0, #75, msl #8
117+
; CHECK-NEXT: ret
118+
entry:
119+
ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>
98120
}
99121

100122
define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp {
101-
entry:
102123
; CHECK-LABEL: movi_4s_imm_t8:
103-
; CHECK: movi.4s v0, #75, msl #16
104-
ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>
124+
; CHECK: // %bb.0: // %entry
125+
; CHECK-NEXT: movi.4s v0, #75, msl #16
126+
; CHECK-NEXT: ret
127+
entry:
128+
ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>
105129
}
106130

107131
define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp {
108-
entry:
109132
; CHECK-LABEL: movi_16b_imm_t9:
110-
; CHECK: movi.16b v0, #75
111-
ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75,
112-
i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>
133+
; CHECK: // %bb.0: // %entry
134+
; CHECK-NEXT: movi.16b v0, #75
135+
; CHECK-NEXT: ret
136+
entry:
137+
ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>
113138
}
114139

115140
define <2 x i64> @movi_2d_imm_t10() nounwind readnone ssp {
116-
entry:
117141
; CHECK-LABEL: movi_2d_imm_t10:
118-
; CHECK: movi.2d v0, #0xff00ff00ff00ff
119-
ret <2 x i64> <i64 71777214294589695, i64 71777214294589695>
142+
; CHECK: // %bb.0: // %entry
143+
; CHECK-NEXT: movi.2d v0, #0xff00ff00ff00ff
144+
; CHECK-NEXT: ret
145+
entry:
146+
ret <2 x i64> <i64 71777214294589695, i64 71777214294589695>
120147
}
121148

122149
define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp {
123-
entry:
124150
; CHECK-LABEL: movi_4s_imm_t11:
125-
; CHECK: fmov.4s v0, #-0.32812500
126-
ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088>
151+
; CHECK: // %bb.0: // %entry
152+
; CHECK-NEXT: fmov.4s v0, #-0.32812500
153+
; CHECK-NEXT: ret
154+
entry:
155+
ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088>
127156
}
128157

129158
define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp {
130-
entry:
131159
; CHECK-LABEL: movi_2d_imm_t12:
132-
; CHECK: fmov.2d v0, #-0.17187500
133-
ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664>
160+
; CHECK: // %bb.0: // %entry
161+
; CHECK-NEXT: fmov.2d v0, #-0.17187500
162+
; CHECK-NEXT: ret
163+
entry:
164+
ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664>
134165
}

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