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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 |
| 2 | +; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator \ |
| 3 | +; RUN: -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s |
| 4 | + |
| 5 | +; Any tests that would have identical output for some combination of the ilp32* |
| 6 | +; ABIs belong in calling-conv-*-common.ll. This file contains tests that will |
| 7 | +; have different output across those ABIs. i.e. where some arguments would be |
| 8 | +; passed according to the floating point ABI. |
| 9 | + |
| 10 | +define i32 @callee_float_in_regs(i32 %a, float %b) nounwind { |
| 11 | + ; RV32I-LABEL: name: callee_float_in_regs |
| 12 | + ; RV32I: bb.1 (%ir-block.0): |
| 13 | + ; RV32I-NEXT: liveins: $x10, $x11 |
| 14 | + ; RV32I-NEXT: {{ $}} |
| 15 | + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| 16 | + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 |
| 17 | + ; RV32I-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY1]](s32) |
| 18 | + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[FPTOSI]] |
| 19 | + ; RV32I-NEXT: $x10 = COPY [[ADD]](s32) |
| 20 | + ; RV32I-NEXT: PseudoRET implicit $x10 |
| 21 | + %b_fptosi = fptosi float %b to i32 |
| 22 | + %1 = add i32 %a, %b_fptosi |
| 23 | + ret i32 %1 |
| 24 | +} |
| 25 | + |
| 26 | +define i32 @caller_float_in_regs() nounwind { |
| 27 | + ; RV32I-LABEL: name: caller_float_in_regs |
| 28 | + ; RV32I: bb.1 (%ir-block.0): |
| 29 | + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 |
| 30 | + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00 |
| 31 | + ; RV32I-NEXT: $x10 = COPY [[C]](s32) |
| 32 | + ; RV32I-NEXT: $x11 = COPY [[C1]](s32) |
| 33 | + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_in_regs, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10 |
| 34 | + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| 35 | + ; RV32I-NEXT: $x10 = COPY [[COPY]](s32) |
| 36 | + ; RV32I-NEXT: PseudoRET implicit $x10 |
| 37 | + %1 = call i32 @callee_float_in_regs(i32 1, float 2.0) |
| 38 | + ret i32 %1 |
| 39 | +} |
| 40 | + |
| 41 | +define i32 @callee_float_on_stack(i64 %a, i64 %b, i64 %c, i64 %d, float %e) nounwind { |
| 42 | + ; RV32I-LABEL: name: callee_float_on_stack |
| 43 | + ; RV32I: bb.1 (%ir-block.0): |
| 44 | + ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17 |
| 45 | + ; RV32I-NEXT: {{ $}} |
| 46 | + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| 47 | + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11 |
| 48 | + ; RV32I-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32) |
| 49 | + ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12 |
| 50 | + ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13 |
| 51 | + ; RV32I-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32) |
| 52 | + ; RV32I-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14 |
| 53 | + ; RV32I-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15 |
| 54 | + ; RV32I-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32) |
| 55 | + ; RV32I-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16 |
| 56 | + ; RV32I-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17 |
| 57 | + ; RV32I-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32) |
| 58 | + ; RV32I-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 |
| 59 | + ; RV32I-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16) |
| 60 | + ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV3]](s64) |
| 61 | + ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[LOAD]] |
| 62 | + ; RV32I-NEXT: $x10 = COPY [[ADD]](s32) |
| 63 | + ; RV32I-NEXT: PseudoRET implicit $x10 |
| 64 | + %1 = trunc i64 %d to i32 |
| 65 | + %2 = bitcast float %e to i32 |
| 66 | + %3 = add i32 %1, %2 |
| 67 | + ret i32 %3 |
| 68 | +} |
| 69 | + |
| 70 | +define i32 @caller_float_on_stack() nounwind { |
| 71 | + ; RV32I-LABEL: name: caller_float_on_stack |
| 72 | + ; RV32I: bb.1 (%ir-block.0): |
| 73 | + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 |
| 74 | + ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 |
| 75 | + ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 |
| 76 | + ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4 |
| 77 | + ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 5.000000e+00 |
| 78 | + ; RV32I-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) |
| 79 | + ; RV32I-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64) |
| 80 | + ; RV32I-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64) |
| 81 | + ; RV32I-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64) |
| 82 | + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2 |
| 83 | + ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 |
| 84 | + ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s32) |
| 85 | + ; RV32I-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16) |
| 86 | + ; RV32I-NEXT: $x10 = COPY [[UV]](s32) |
| 87 | + ; RV32I-NEXT: $x11 = COPY [[UV1]](s32) |
| 88 | + ; RV32I-NEXT: $x12 = COPY [[UV2]](s32) |
| 89 | + ; RV32I-NEXT: $x13 = COPY [[UV3]](s32) |
| 90 | + ; RV32I-NEXT: $x14 = COPY [[UV4]](s32) |
| 91 | + ; RV32I-NEXT: $x15 = COPY [[UV5]](s32) |
| 92 | + ; RV32I-NEXT: $x16 = COPY [[UV6]](s32) |
| 93 | + ; RV32I-NEXT: $x17 = COPY [[UV7]](s32) |
| 94 | + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_float_on_stack, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x10 |
| 95 | + ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10 |
| 96 | + ; RV32I-NEXT: $x10 = COPY [[COPY1]](s32) |
| 97 | + ; RV32I-NEXT: PseudoRET implicit $x10 |
| 98 | + %1 = call i32 @callee_float_on_stack(i64 1, i64 2, i64 3, i64 4, float 5.0) |
| 99 | + ret i32 %1 |
| 100 | +} |
| 101 | + |
| 102 | +define float @callee_tiny_scalar_ret() nounwind { |
| 103 | + ; RV32I-LABEL: name: callee_tiny_scalar_ret |
| 104 | + ; RV32I: bb.1 (%ir-block.0): |
| 105 | + ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 |
| 106 | + ; RV32I-NEXT: $x10 = COPY [[C]](s32) |
| 107 | + ; RV32I-NEXT: PseudoRET implicit $x10 |
| 108 | + ret float 1.0 |
| 109 | +} |
| 110 | + |
| 111 | +define i32 @caller_tiny_scalar_ret() nounwind { |
| 112 | + ; RV32I-LABEL: name: caller_tiny_scalar_ret |
| 113 | + ; RV32I: bb.1 (%ir-block.0): |
| 114 | + ; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_tiny_scalar_ret, implicit-def $x1, implicit-def $x10 |
| 115 | + ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10 |
| 116 | + ; RV32I-NEXT: $x10 = COPY [[COPY]](s32) |
| 117 | + ; RV32I-NEXT: PseudoRET implicit $x10 |
| 118 | + %1 = call float @callee_tiny_scalar_ret() |
| 119 | + %2 = bitcast float %1 to i32 |
| 120 | + ret i32 %2 |
| 121 | +} |
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