Update llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir

Author: ritter-x2a

llvm/test/CodeGen/AMDGPU/peephole-opt-fold-reg-sequence-subreg.mir

@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -run-pass=peephole-opt -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass=peephole-opt -o - %s | FileCheck %s
 
 ---
 name:            reg_sequence_extract_subreg_sub0_from_regsequence_sub0_sub1