Skip to content

Commit d9507a3

Browse files
authored
[DAGCombine] Fix miscompilation caused by PR94008 (#94850)
The pr description in #94008 mismatches with the code. > + When VT is smaller than ShiftVT, it is safe to use trunc. > + When VT is larger than ShiftVT, it is safe to use zext iff `is_zero_poison` is true (i.e., `opcode == ISD::CTTZ_ZERO_UNDEF`). See also the counterexample `src_shl_cttz2 -> tgt_shl_cttz2` in the alive2 proofs. Closes #94824.
1 parent 2d21851 commit d9507a3

File tree

2 files changed

+20
-1
lines changed

2 files changed

+20
-1
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10112,7 +10112,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
1011210112
// fold (shl X, cttz(Y)) -> (mul (Y & -Y), X) if cttz is unsupported on the
1011310113
// target.
1011410114
if (((N1.getOpcode() == ISD::CTTZ &&
10115-
VT.getScalarSizeInBits() >= ShiftVT.getScalarSizeInBits()) ||
10115+
VT.getScalarSizeInBits() <= ShiftVT.getScalarSizeInBits()) ||
1011610116
N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
1011710117
N1.hasOneUse() && !TLI.isOperationLegalOrCustom(ISD::CTTZ, ShiftVT) &&
1011810118
TLI.isOperationLegalOrCustom(ISD::MUL, VT)) {

llvm/test/CodeGen/X86/pr94824.ll

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
3+
4+
define i16 @pr94824(i8 %x1) {
5+
; CHECK-LABEL: pr94824:
6+
; CHECK: # %bb.0: # %entry
7+
; CHECK-NEXT: orl $256, %edi # imm = 0x100
8+
; CHECK-NEXT: rep bsfl %edi, %ecx
9+
; CHECK-NEXT: movl $1, %eax
10+
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
11+
; CHECK-NEXT: shll %cl, %eax
12+
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
13+
; CHECK-NEXT: retq
14+
entry:
15+
%cttz = call i8 @llvm.cttz.i8(i8 %x1, i1 false)
16+
%ext = zext i8 %cttz to i16
17+
%shl = shl i16 1, %ext
18+
ret i16 %shl
19+
}

0 commit comments

Comments
 (0)