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AMDGPU: Simplify some tests by not using amdgpu_ps
Since inreg now works for the default calling convention, we can check the output with fewer argument shuffling instructions.
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2 files changed

+45
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‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.fadd.ll

+25-35
Original file line numberDiff line numberDiff line change
@@ -1,68 +1,58 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 < %s | FileCheck -check-prefix=CHECK %s
33

4-
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
4+
define void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
55
; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
66
; CHECK: ; %bb.0:
7-
; CHECK-NEXT: s_mov_b32 s11, s5
8-
; CHECK-NEXT: s_mov_b32 s10, s4
9-
; CHECK-NEXT: s_mov_b32 s9, s3
10-
; CHECK-NEXT: s_mov_b32 s8, s2
11-
; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[8:11], s6 offen offset:24
12-
; CHECK-NEXT: s_endpgm
7+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8+
; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[4:7], s8 offen offset:24
9+
; CHECK-NEXT: s_waitcnt vmcnt(0)
10+
; CHECK-NEXT: s_setpc_b64 s[30:31]
1311
%voffset.add = add i32 %voffset, 24
1412
%ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset.add, i32 %soffset, i32 0)
1513
ret void
1614
}
1715

18-
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
16+
define void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 inreg %soffset) {
1917
; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
2018
; CHECK: ; %bb.0:
21-
; CHECK-NEXT: s_mov_b32 s11, s5
22-
; CHECK-NEXT: s_mov_b32 s10, s4
23-
; CHECK-NEXT: s_mov_b32 s9, s3
24-
; CHECK-NEXT: s_mov_b32 s8, s2
25-
; CHECK-NEXT: buffer_atomic_add_f32 v0, off, s[8:11], s6
26-
; CHECK-NEXT: s_endpgm
19+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20+
; CHECK-NEXT: buffer_atomic_add_f32 v0, off, s[4:7], s8
21+
; CHECK-NEXT: s_waitcnt vmcnt(0)
22+
; CHECK-NEXT: s_setpc_b64 s[30:31]
2723
%ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
2824
ret void
2925
}
3026

31-
define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
27+
define void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
3228
; CHECK-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
3329
; CHECK: ; %bb.0:
34-
; CHECK-NEXT: s_mov_b32 s11, s5
35-
; CHECK-NEXT: s_mov_b32 s10, s4
36-
; CHECK-NEXT: s_mov_b32 s9, s3
37-
; CHECK-NEXT: s_mov_b32 s8, s2
38-
; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[8:11], s6 offen
39-
; CHECK-NEXT: s_endpgm
30+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
31+
; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, v1, s[4:7], s8 offen
32+
; CHECK-NEXT: s_waitcnt vmcnt(0)
33+
; CHECK-NEXT: s_setpc_b64 s[30:31]
4034
%ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
4135
ret void
4236
}
4337

44-
define amdgpu_ps void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
38+
define void @raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
4539
; CHECK-LABEL: raw_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
4640
; CHECK: ; %bb.0:
47-
; CHECK-NEXT: s_mov_b32 s11, s5
48-
; CHECK-NEXT: s_mov_b32 s10, s4
49-
; CHECK-NEXT: s_mov_b32 s9, s3
50-
; CHECK-NEXT: s_mov_b32 s8, s2
51-
; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, off, s[8:11], s6 offset:92
52-
; CHECK-NEXT: s_endpgm
41+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
42+
; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, off, s[4:7], s8 offset:92
43+
; CHECK-NEXT: s_waitcnt vmcnt(0)
44+
; CHECK-NEXT: s_setpc_b64 s[30:31]
5345
%ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 92, i32 %soffset, i32 0)
5446
ret void
5547
}
5648

57-
define amdgpu_ps void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
49+
define void @raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
5850
; CHECK-LABEL: raw_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
5951
; CHECK: ; %bb.0:
60-
; CHECK-NEXT: s_mov_b32 s11, s5
61-
; CHECK-NEXT: s_mov_b32 s10, s4
62-
; CHECK-NEXT: s_mov_b32 s9, s3
63-
; CHECK-NEXT: s_mov_b32 s8, s2
64-
; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[8:11], s6 offen slc
65-
; CHECK-NEXT: s_endpgm
52+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
53+
; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[4:7], s8 offen slc
54+
; CHECK-NEXT: s_waitcnt vmcnt(0)
55+
; CHECK-NEXT: s_setpc_b64 s[30:31]
6656
%ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2)
6757
ret void
6858
}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.fadd.ll

+20-28
Original file line numberDiff line numberDiff line change
@@ -1,56 +1,48 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx908 < %s | FileCheck %s -check-prefix=CHECK
33

4-
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
4+
define void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
55
; CHECK-LABEL: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
66
; CHECK: ; %bb.0:
7-
; CHECK-NEXT: s_mov_b32 s11, s5
8-
; CHECK-NEXT: s_mov_b32 s10, s4
9-
; CHECK-NEXT: s_mov_b32 s9, s3
10-
; CHECK-NEXT: s_mov_b32 s8, s2
11-
; CHECK-NEXT: buffer_atomic_add_f32 v0, v[1:2], s[8:11], s6 idxen offen offset:24
12-
; CHECK-NEXT: s_endpgm
7+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8+
; CHECK-NEXT: buffer_atomic_add_f32 v0, v[1:2], s[4:7], s8 idxen offen offset:24
9+
; CHECK-NEXT: s_waitcnt vmcnt(0)
10+
; CHECK-NEXT: s_setpc_b64 s[30:31]
1311
%voffset.add = add i32 %voffset, 24
1412
%ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)
1513
ret void
1614
}
1715

1816
; Natural mapping, no voffset
19-
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {
17+
define void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 inreg %soffset) {
2018
; CHECK-LABEL: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__0_voffset__sgpr_soffset:
2119
; CHECK: ; %bb.0:
22-
; CHECK-NEXT: s_mov_b32 s11, s5
23-
; CHECK-NEXT: s_mov_b32 s10, s4
24-
; CHECK-NEXT: s_mov_b32 s9, s3
25-
; CHECK-NEXT: s_mov_b32 s8, s2
26-
; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[8:11], s6 idxen
27-
; CHECK-NEXT: s_endpgm
20+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
21+
; CHECK-NEXT: buffer_atomic_add_f32 v0, v1, s[4:7], s8 idxen
22+
; CHECK-NEXT: s_waitcnt vmcnt(0)
23+
; CHECK-NEXT: s_setpc_b64 s[30:31]
2824
%ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 %soffset, i32 0)
2925
ret void
3026
}
3127

32-
define amdgpu_ps void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
28+
define void @struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc(float %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
3329
; CHECK-LABEL: struct_buffer_atomic_add_f32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc:
3430
; CHECK: ; %bb.0:
35-
; CHECK-NEXT: s_mov_b32 s11, s5
36-
; CHECK-NEXT: s_mov_b32 s10, s4
37-
; CHECK-NEXT: s_mov_b32 s9, s3
38-
; CHECK-NEXT: s_mov_b32 s8, s2
39-
; CHECK-NEXT: buffer_atomic_add_f32 v0, v[1:2], s[8:11], s6 idxen offen slc
40-
; CHECK-NEXT: s_endpgm
31+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
32+
; CHECK-NEXT: buffer_atomic_add_f32 v0, v[1:2], s[4:7], s8 idxen offen slc
33+
; CHECK-NEXT: s_waitcnt vmcnt(0)
34+
; CHECK-NEXT: s_setpc_b64 s[30:31]
4135
%ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 2)
4236
ret void
4337
}
4438

45-
define amdgpu_ps void @struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
39+
define void @struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
4640
; CHECK-LABEL: struct_buffer_atomic_add_v2f16_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset:
4741
; CHECK: ; %bb.0:
48-
; CHECK-NEXT: s_mov_b32 s11, s5
49-
; CHECK-NEXT: s_mov_b32 s10, s4
50-
; CHECK-NEXT: s_mov_b32 s9, s3
51-
; CHECK-NEXT: s_mov_b32 s8, s2
52-
; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, v[1:2], s[8:11], s6 idxen offen offset:24
53-
; CHECK-NEXT: s_endpgm
42+
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
43+
; CHECK-NEXT: buffer_atomic_pk_add_f16 v0, v[1:2], s[4:7], s8 idxen offen offset:24
44+
; CHECK-NEXT: s_waitcnt vmcnt(0)
45+
; CHECK-NEXT: s_setpc_b64 s[30:31]
5446
%voffset.add = add i32 %voffset, 24
5547
%ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset.add, i32 %soffset, i32 0)
5648
ret void

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