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[CodeGen] Add generic INIT_UNDEF pseudo
The InitUndef pass currently uses target-specific pseudo instructions, with one pseudo per register class. Instead, add a generic pseudo instruction, which can be used by all targets and register classes.
1 parent eaf87d3 commit dcc82f5

16 files changed

+118
-172
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2278,15 +2278,6 @@ class TargetInstrInfo : public MCInstrInfo {
22782278
llvm_unreachable("unknown number of operands necessary");
22792279
}
22802280

2281-
/// Gets the opcode for the Pseudo Instruction used to initialize
2282-
/// the undef value. If no Instruction is available, this will
2283-
/// fail compilation.
2284-
virtual unsigned getUndefInitOpcode(unsigned RegClassID) const {
2285-
(void)RegClassID;
2286-
2287-
llvm_unreachable("Unexpected register class.");
2288-
}
2289-
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private:
22912282
mutable std::unique_ptr<MIRFormatter> Formatter;
22922283
unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;

‎llvm/include/llvm/Support/TargetOpcodes.def

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,11 @@ HANDLE_TARGET_OPCODE(INSERT_SUBREG)
5656
/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
5757
HANDLE_TARGET_OPCODE(IMPLICIT_DEF)
5858

59+
/// Explicit undef initialization used past IMPLICIT_DEF elimination in cases
60+
/// where an undef operand must be allocated to a different register than an
61+
/// early-clobber result operand.
62+
HANDLE_TARGET_OPCODE(INIT_UNDEF)
63+
5964
/// SUBREG_TO_REG - Assert the value of bits in a super register.
6065
/// The result of this instruction is the value of the second operand inserted
6166
/// into the subregister specified by the third operand. All other bits are

‎llvm/include/llvm/Target/Target.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1254,6 +1254,13 @@ def IMPLICIT_DEF : StandardPseudoInstruction {
12541254
let isAsCheapAsAMove = true;
12551255
let isMeta = true;
12561256
}
1257+
def INIT_UNDEF : StandardPseudoInstruction {
1258+
let OutOperandList = (outs unknown:$dst);
1259+
let InOperandList = (ins);
1260+
let AsmString = "";
1261+
let hasSideEffects = false;
1262+
let Size = 0;
1263+
}
12571264
def SUBREG_TO_REG : StandardPseudoInstruction {
12581265
let OutOperandList = (outs unknown:$dst);
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let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);

‎llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1832,6 +1832,10 @@ void AsmPrinter::emitFunctionBody() {
18321832
// This instruction is only used to note jump table debug info, it's
18331833
// purely meta information.
18341834
break;
1835+
case TargetOpcode::INIT_UNDEF:
1836+
// This is only used to influence register allocation behavior, no
1837+
// actual initialization is needed.
1838+
break;
18351839
default:
18361840
emitInstruction(&MI);
18371841
if (CanDoExtraAnalysis) {

‎llvm/lib/CodeGen/InitUndef.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -177,8 +177,7 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
177177
Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);
178178
LLVM_DEBUG(dbgs() << "Register Class ID" << SubRegClass->getID() << "\n");
179179
BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
180-
TII->get(TII->getUndefInitOpcode(SubRegClass->getID())),
181-
TmpInitSubReg);
180+
TII->get(TargetOpcode::INIT_UNDEF), TmpInitSubReg);
182181
Register NewReg = MRI->createVirtualRegister(TargetRegClass);
183182
BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
184183
TII->get(TargetOpcode::INSERT_SUBREG), NewReg)
@@ -203,9 +202,9 @@ bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {
203202
const TargetRegisterClass *TargetRegClass =
204203
TRI->getLargestSuperClass(MRI->getRegClass(MO.getReg()));
205204
LLVM_DEBUG(dbgs() << "Register Class ID" << TargetRegClass->getID() << "\n");
206-
unsigned Opcode = TII->getUndefInitOpcode(TargetRegClass->getID());
207205
Register NewReg = MRI->createVirtualRegister(TargetRegClass);
208-
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(Opcode), NewReg);
206+
BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
207+
TII->get(TargetOpcode::INIT_UNDEF), NewReg);
209208
MO.setReg(NewReg);
210209
if (MO.isUndef())
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MO.setIsUndef(false);

‎llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2411,12 +2411,6 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
24112411
case ARM::SEH_EpilogEnd:
24122412
ATS.emitARMWinCFIEpilogEnd();
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return;
2414-
2415-
case ARM::PseudoARMInitUndefMQPR:
2416-
case ARM::PseudoARMInitUndefSPR:
2417-
case ARM::PseudoARMInitUndefDPR_VFP2:
2418-
case ARM::PseudoARMInitUndefGPR:
2419-
return;
24202414
}
24212415

24222416
MCInst TmpInst;

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -546,19 +546,6 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
546546

547547
std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
548548
Register Reg) const override;
549-
550-
unsigned getUndefInitOpcode(unsigned RegClassID) const override {
551-
if (RegClassID == ARM::MQPRRegClass.getID())
552-
return ARM::PseudoARMInitUndefMQPR;
553-
if (RegClassID == ARM::SPRRegClass.getID())
554-
return ARM::PseudoARMInitUndefSPR;
555-
if (RegClassID == ARM::DPR_VFP2RegClass.getID())
556-
return ARM::PseudoARMInitUndefDPR_VFP2;
557-
if (RegClassID == ARM::GPRRegClass.getID())
558-
return ARM::PseudoARMInitUndefGPR;
559-
560-
llvm_unreachable("Unexpected register class.");
561-
}
562549
};
563550

564551
/// Get the operands corresponding to the given \p Pred value. By default, the

‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -6536,15 +6536,3 @@ let isPseudo = 1 in {
65366536
let isTerminator = 1 in
65376537
def SEH_EpilogEnd : PseudoInst<(outs), (ins), NoItinerary, []>, Sched<[]>;
65386538
}
6539-
6540-
6541-
//===----------------------------------------------------------------------===//
6542-
// Pseudo Instructions for use when early-clobber is defined and Greedy Register
6543-
// Allocation is used. This ensures the constraint is used properly.
6544-
//===----------------------------------------------------------------------===//
6545-
let isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
6546-
def PseudoARMInitUndefMQPR : PseudoInst<(outs MQPR:$vd), (ins), NoItinerary, []>;
6547-
def PseudoARMInitUndefSPR : PseudoInst<(outs SPR:$sd), (ins), NoItinerary, []>;
6548-
def PseudoARMInitUndefDPR_VFP2 : PseudoInst<(outs DPR_VFP2:$dd), (ins), NoItinerary, []>;
6549-
def PseudoARMInitUndefGPR : PseudoInst<(outs GPR:$rd), (ins), NoItinerary, []>;
6550-
}

‎llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -303,11 +303,6 @@ void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
303303
case RISCV::KCFI_CHECK:
304304
LowerKCFI_CHECK(*MI);
305305
return;
306-
case RISCV::PseudoRVVInitUndefM1:
307-
case RISCV::PseudoRVVInitUndefM2:
308-
case RISCV::PseudoRVVInitUndefM4:
309-
case RISCV::PseudoRVVInitUndefM8:
310-
return;
311306
case TargetOpcode::STACKMAP:
312307
return LowerSTACKMAP(*OutStreamer, SM, *MI);
313308
case TargetOpcode::PATCHPOINT:

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -293,21 +293,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
293293

294294
unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const override;
295295

296-
unsigned getUndefInitOpcode(unsigned RegClassID) const override {
297-
switch (RegClassID) {
298-
case RISCV::VRRegClassID:
299-
return RISCV::PseudoRVVInitUndefM1;
300-
case RISCV::VRM2RegClassID:
301-
return RISCV::PseudoRVVInitUndefM2;
302-
case RISCV::VRM4RegClassID:
303-
return RISCV::PseudoRVVInitUndefM4;
304-
case RISCV::VRM8RegClassID:
305-
return RISCV::PseudoRVVInitUndefM8;
306-
default:
307-
llvm_unreachable("Unexpected register class.");
308-
}
309-
}
310-
311296
protected:
312297
const RISCVSubtarget &STI;
313298

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -6116,15 +6116,6 @@ foreach lmul = MxList in {
61166116
}
61176117
}
61186118

6119-
/// Empty pseudo for RISCVInitUndefPass
6120-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 0,
6121-
isCodeGenOnly = 1 in {
6122-
def PseudoRVVInitUndefM1 : Pseudo<(outs VR:$vd), (ins), [], "">;
6123-
def PseudoRVVInitUndefM2 : Pseudo<(outs VRM2:$vd), (ins), [], "">;
6124-
def PseudoRVVInitUndefM4 : Pseudo<(outs VRM4:$vd), (ins), [], "">;
6125-
def PseudoRVVInitUndefM8 : Pseudo<(outs VRM8:$vd), (ins), [], "">;
6126-
}
6127-
61286119
//===----------------------------------------------------------------------===//
61296120
// 6. Configuration-Setting Instructions
61306121
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/rvv/handle-noreg-with-implicit-def.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ body: |
99
; MIR-LABEL: name: vrgather_all_undef
1010
; MIR: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
1111
; MIR-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
12-
; MIR-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
13-
; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF1]], killed [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
12+
; MIR-NEXT: [[INIT_UNDEF:%[0-9]+]]:vr = INIT_UNDEF
13+
; MIR-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 [[DEF1]], killed [[INIT_UNDEF]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
1414
; MIR-NEXT: $v8 = COPY %1
1515
; MIR-NEXT: PseudoRET implicit $v8
1616
%2:vr = IMPLICIT_DEF

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