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[RISCV] Remove vfmv.s.f and vfmv.f.s lmul pseudo variants (#100970)
In #71501 we removed the LMUL variants for vmv.s.x and vmv.x.s because they ignore register groups, so this patch does the same for their floating point equivalents. We don't need to add any extra patterns for extractelt in RISCVInstrInfoVSDPatterns.td because in lowerEXTRACT_VECTOR_ELT we make sure that the node is narrowed down to LMUL 1.
1 parent d230442 commit e106537

18 files changed

+89
-97
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,7 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
458458
}
459459
}
460460

461-
// vmv.x.s, and vmv.f.s are unconditional and ignore everything except SEW.
461+
// vmv.x.s, and vfmv.f.s are unconditional and ignore everything except SEW.
462462
if (isScalarExtractInstr(MI)) {
463463
assert(!RISCVII::hasVLOp(TSFlags));
464464
Res.LMUL = DemandedFields::LMULNone;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6781,26 +6781,20 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
67816781
let Predicates = [HasVInstructionsAnyF] in {
67826782
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
67836783
foreach f = FPList in {
6784-
foreach m = f.MxList in {
6785-
defvar mx = m.MX;
6786-
let VLMul = m.value in {
6787-
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
6788-
def "PseudoVFMV_" # f.FX # "_S_" # mx :
6789-
Pseudo<(outs f.fprclass:$rd),
6790-
(ins m.vrclass:$rs2, ixlenimm:$sew), []>,
6791-
Sched<[WriteVMovFS, ReadVMovFS]>,
6792-
RISCVVPseudo;
6793-
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
6794-
Constraints = "$rd = $rs1" in
6795-
def "PseudoVFMV_S_" # f.FX # "_" # mx :
6796-
Pseudo<(outs m.vrclass:$rd),
6797-
(ins m.vrclass:$rs1, f.fprclass:$rs2,
6798-
AVL:$vl, ixlenimm:$sew),
6799-
[]>,
6800-
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>,
6801-
RISCVVPseudo;
6802-
}
6803-
}
6784+
let HasSEWOp = 1, BaseInstr = VFMV_F_S in
6785+
def "PseudoVFMV_" # f.FX # "_S" :
6786+
Pseudo<(outs f.fprclass:$rd),
6787+
(ins VR:$rs2, ixlenimm:$sew), []>,
6788+
Sched<[WriteVMovFS, ReadVMovFS]>,
6789+
RISCVVPseudo;
6790+
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
6791+
Constraints = "$rd = $rs1" in
6792+
def "PseudoVFMV_S_" # f.FX :
6793+
Pseudo<(outs VR:$rd),
6794+
(ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, ixlenimm:$sew),
6795+
[]>,
6796+
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>,
6797+
RISCVVPseudo;
68046798
}
68056799
}
68066800
} // Predicates = [HasVInstructionsAnyF]

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1444,14 +1444,14 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
14441444
//===----------------------------------------------------------------------===//
14451445
// Vector Element Extracts
14461446
//===----------------------------------------------------------------------===//
1447-
foreach vti = AllFloatVectors in {
1448-
defvar vmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",
1447+
foreach vti = NoGroupFloatVectors in {
1448+
defvar vfmv_f_s_inst = !cast<Instruction>(!strconcat("PseudoVFMV_",
14491449
vti.ScalarSuffix,
1450-
"_S_", vti.LMul.MX));
1450+
"_S"));
14511451
// Only pattern-match extract-element operations where the index is 0. Any
14521452
// other index will have been custom-lowered to slide the vector correctly
14531453
// into place.
14541454
let Predicates = GetVTypePredicates<vti>.Predicates in
14551455
def : Pat<(vti.Scalar (extractelt (vti.Vector vti.RegClass:$rs2), 0)),
1456-
(vmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>;
1456+
(vfmv_f_s_inst vti.RegClass:$rs2, vti.Log2SEW)>;
14571457
}

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2934,18 +2934,16 @@ foreach vti = NoGroupFloatVectors in {
29342934
(vti.Scalar (SelectFPImm (XLenVT GPR:$imm))),
29352935
VLOpFrag)),
29362936
(PseudoVMV_S_X $merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>;
2937-
}
2938-
}
2939-
2940-
foreach vti = AllFloatVectors in {
2941-
let Predicates = GetVTypePredicates<vti>.Predicates in {
29422937
def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
29432938
vti.ScalarRegClass:$rs1,
29442939
VLOpFrag)),
2945-
(!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX)
2940+
(!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix)
29462941
vti.RegClass:$merge,
29472942
(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
29482943
}
2944+
}
2945+
2946+
foreach vti = AllFloatVectors in {
29492947
defvar ivti = GetIntVTypeInfo<vti>.Vti;
29502948
let Predicates = GetVTypePredicates<ivti>.Predicates in {
29512949
def : Pat<(vti.Vector

‎llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
define half @extractelt_nxv1f16_0(<vscale x 1 x half> %v) {
88
; CHECK-LABEL: extractelt_nxv1f16_0:
99
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
10+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
1111
; CHECK-NEXT: vfmv.f.s fa0, v8
1212
; CHECK-NEXT: ret
1313
%r = extractelement <vscale x 1 x half> %v, i32 0
@@ -39,7 +39,7 @@ define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 zeroext %idx) {
3939
define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) {
4040
; CHECK-LABEL: extractelt_nxv2f16_0:
4141
; CHECK: # %bb.0:
42-
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
42+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
4343
; CHECK-NEXT: vfmv.f.s fa0, v8
4444
; CHECK-NEXT: ret
4545
%r = extractelement <vscale x 2 x half> %v, i32 0
@@ -199,7 +199,7 @@ define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 zeroext %idx)
199199
define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) {
200200
; CHECK-LABEL: extractelt_nxv1f32_0:
201201
; CHECK: # %bb.0:
202-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
202+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
203203
; CHECK-NEXT: vfmv.f.s fa0, v8
204204
; CHECK-NEXT: ret
205205
%r = extractelement <vscale x 1 x float> %v, i32 0

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -265,13 +265,13 @@ define i64 @bitcast_v1i64_i64(<1 x i64> %a) {
265265
define half @bitcast_v2i8_f16(<2 x i8> %a) {
266266
; CHECK-LABEL: bitcast_v2i8_f16:
267267
; CHECK: # %bb.0:
268-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
268+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
269269
; CHECK-NEXT: vfmv.f.s fa0, v8
270270
; CHECK-NEXT: ret
271271
;
272272
; ELEN32-LABEL: bitcast_v2i8_f16:
273273
; ELEN32: # %bb.0:
274-
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
274+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
275275
; ELEN32-NEXT: vfmv.f.s fa0, v8
276276
; ELEN32-NEXT: ret
277277
%b = bitcast <2 x i8> %a to half
@@ -281,13 +281,13 @@ define half @bitcast_v2i8_f16(<2 x i8> %a) {
281281
define half @bitcast_v1i16_f16(<1 x i16> %a) {
282282
; CHECK-LABEL: bitcast_v1i16_f16:
283283
; CHECK: # %bb.0:
284-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
284+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
285285
; CHECK-NEXT: vfmv.f.s fa0, v8
286286
; CHECK-NEXT: ret
287287
;
288288
; ELEN32-LABEL: bitcast_v1i16_f16:
289289
; ELEN32: # %bb.0:
290-
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
290+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
291291
; ELEN32-NEXT: vfmv.f.s fa0, v8
292292
; ELEN32-NEXT: ret
293293
%b = bitcast <1 x i16> %a to half
@@ -297,7 +297,7 @@ define half @bitcast_v1i16_f16(<1 x i16> %a) {
297297
define float @bitcast_v4i8_f32(<4 x i8> %a) {
298298
; CHECK-LABEL: bitcast_v4i8_f32:
299299
; CHECK: # %bb.0:
300-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
300+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
301301
; CHECK-NEXT: vfmv.f.s fa0, v8
302302
; CHECK-NEXT: ret
303303
;
@@ -313,7 +313,7 @@ define float @bitcast_v4i8_f32(<4 x i8> %a) {
313313
define float @bitcast_v2i16_f32(<2 x i16> %a) {
314314
; CHECK-LABEL: bitcast_v2i16_f32:
315315
; CHECK: # %bb.0:
316-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
316+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
317317
; CHECK-NEXT: vfmv.f.s fa0, v8
318318
; CHECK-NEXT: ret
319319
;
@@ -329,7 +329,7 @@ define float @bitcast_v2i16_f32(<2 x i16> %a) {
329329
define float @bitcast_v1i32_f32(<1 x i32> %a) {
330330
; CHECK-LABEL: bitcast_v1i32_f32:
331331
; CHECK: # %bb.0:
332-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
332+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
333333
; CHECK-NEXT: vfmv.f.s fa0, v8
334334
; CHECK-NEXT: ret
335335
;

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ define i16 @bitcast_v1f16_i16(<1 x half> %a) {
1919
define half @bitcast_v1f16_f16(<1 x half> %a) {
2020
; CHECK-LABEL: bitcast_v1f16_f16:
2121
; CHECK: # %bb.0:
22-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
22+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
2323
; CHECK-NEXT: vfmv.f.s fa0, v8
2424
; CHECK-NEXT: ret
2525
%b = bitcast <1 x half> %a to half
@@ -49,7 +49,7 @@ define i32 @bitcast_v1f32_i32(<1 x float> %a) {
4949
define float @bitcast_v2f16_f32(<2 x half> %a) {
5050
; CHECK-LABEL: bitcast_v2f16_f32:
5151
; CHECK: # %bb.0:
52-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
52+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
5353
; CHECK-NEXT: vfmv.f.s fa0, v8
5454
; CHECK-NEXT: ret
5555
%b = bitcast <2 x half> %a to float
@@ -59,7 +59,7 @@ define float @bitcast_v2f16_f32(<2 x half> %a) {
5959
define float @bitcast_v1f32_f32(<1 x float> %a) {
6060
; CHECK-LABEL: bitcast_v1f32_f32:
6161
; CHECK: # %bb.0:
62-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
62+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
6363
; CHECK-NEXT: vfmv.f.s fa0, v8
6464
; CHECK-NEXT: ret
6565
%b = bitcast <1 x float> %a to float
@@ -237,7 +237,7 @@ define <1 x double> @bitcast_i64_v1f64(i64 %a) {
237237
define <1 x i16> @bitcast_f16_v1i16(half %a) {
238238
; CHECK-LABEL: bitcast_f16_v1i16:
239239
; CHECK: # %bb.0:
240-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
240+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
241241
; CHECK-NEXT: vfmv.s.f v8, fa0
242242
; CHECK-NEXT: ret
243243
%b = bitcast half %a to <1 x i16>
@@ -247,7 +247,7 @@ define <1 x i16> @bitcast_f16_v1i16(half %a) {
247247
define <1 x half> @bitcast_f16_v1f16(half %a) {
248248
; CHECK-LABEL: bitcast_f16_v1f16:
249249
; CHECK: # %bb.0:
250-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
250+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
251251
; CHECK-NEXT: vfmv.s.f v8, fa0
252252
; CHECK-NEXT: ret
253253
%b = bitcast half %a to <1 x half>
@@ -257,7 +257,7 @@ define <1 x half> @bitcast_f16_v1f16(half %a) {
257257
define <2 x i16> @bitcast_f32_v2i16(float %a) {
258258
; CHECK-LABEL: bitcast_f32_v2i16:
259259
; CHECK: # %bb.0:
260-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
260+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
261261
; CHECK-NEXT: vfmv.s.f v8, fa0
262262
; CHECK-NEXT: ret
263263
%b = bitcast float %a to <2 x i16>
@@ -267,7 +267,7 @@ define <2 x i16> @bitcast_f32_v2i16(float %a) {
267267
define <2 x half> @bitcast_f32_v2f16(float %a) {
268268
; CHECK-LABEL: bitcast_f32_v2f16:
269269
; CHECK: # %bb.0:
270-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
270+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
271271
; CHECK-NEXT: vfmv.s.f v8, fa0
272272
; CHECK-NEXT: ret
273273
%b = bitcast float %a to <2 x half>
@@ -277,7 +277,7 @@ define <2 x half> @bitcast_f32_v2f16(float %a) {
277277
define <1 x i32> @bitcast_f32_v1i32(float %a) {
278278
; CHECK-LABEL: bitcast_f32_v1i32:
279279
; CHECK: # %bb.0:
280-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
280+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
281281
; CHECK-NEXT: vfmv.s.f v8, fa0
282282
; CHECK-NEXT: ret
283283
%b = bitcast float %a to <1 x i32>
@@ -287,7 +287,7 @@ define <1 x i32> @bitcast_f32_v1i32(float %a) {
287287
define <1 x float> @bitcast_f32_v1f32(float %a) {
288288
; CHECK-LABEL: bitcast_f32_v1f32:
289289
; CHECK: # %bb.0:
290-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
290+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
291291
; CHECK-NEXT: vfmv.s.f v8, fa0
292292
; CHECK-NEXT: ret
293293
%b = bitcast float %a to <1 x float>

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {
1111
; RV32-NEXT: .cfi_def_cfa_offset 16
1212
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1313
; RV32-NEXT: .cfi_offset ra, -4
14-
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
14+
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
1515
; RV32-NEXT: vfmv.f.s fa0, v8
1616
; RV32-NEXT: call llrintf
1717
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
@@ -23,10 +23,10 @@ define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) {
2323
;
2424
; RV64-LABEL: llrint_v1i64_v1f32:
2525
; RV64: # %bb.0:
26-
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
26+
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
2727
; RV64-NEXT: vfmv.f.s fa5, v8
2828
; RV64-NEXT: fcvt.l.s a0, fa5
29-
; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
29+
; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
3030
; RV64-NEXT: vmv.s.x v8, a0
3131
; RV64-NEXT: ret
3232
%a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)
@@ -47,7 +47,7 @@ define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) {
4747
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 2 * vlenb
4848
; RV32-NEXT: addi a0, sp, 16
4949
; RV32-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
50-
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
50+
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
5151
; RV32-NEXT: vfmv.f.s fa0, v8
5252
; RV32-NEXT: call llrintf
5353
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,26 +9,26 @@
99
define <1 x iXLen> @lrint_v1f32(<1 x float> %x) {
1010
; RV32-LABEL: lrint_v1f32:
1111
; RV32: # %bb.0:
12-
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
12+
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
1313
; RV32-NEXT: vfmv.f.s fa5, v8
1414
; RV32-NEXT: fcvt.w.s a0, fa5
1515
; RV32-NEXT: vmv.s.x v8, a0
1616
; RV32-NEXT: ret
1717
;
1818
; RV64-i32-LABEL: lrint_v1f32:
1919
; RV64-i32: # %bb.0:
20-
; RV64-i32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
20+
; RV64-i32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
2121
; RV64-i32-NEXT: vfmv.f.s fa5, v8
2222
; RV64-i32-NEXT: fcvt.l.s a0, fa5
2323
; RV64-i32-NEXT: vmv.s.x v8, a0
2424
; RV64-i32-NEXT: ret
2525
;
2626
; RV64-i64-LABEL: lrint_v1f32:
2727
; RV64-i64: # %bb.0:
28-
; RV64-i64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
28+
; RV64-i64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
2929
; RV64-i64-NEXT: vfmv.f.s fa5, v8
3030
; RV64-i64-NEXT: fcvt.l.s a0, fa5
31-
; RV64-i64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
31+
; RV64-i64-NEXT: vsetvli zero, zero, e64, m2, ta, ma
3232
; RV64-i64-NEXT: vmv.s.x v8, a0
3333
; RV64-i64-NEXT: ret
3434
%a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f32(<1 x float> %x)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ declare half @llvm.vp.reduce.fadd.v2f16(half, <2 x half>, <2 x i1>, i32)
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define half @vpreduce_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fadd_v2f16:
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; ZVFH: # %bb.0:
16-
; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
16+
; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; ZVFH-NEXT: vfredusum.vs v9, v8, v9, v0.t
@@ -39,7 +39,7 @@ define half @vpreduce_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroex
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define half @vpreduce_ord_fadd_v2f16(half %s, <2 x half> %v, <2 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_ord_fadd_v2f16:
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; ZVFH: # %bb.0:
42-
; ZVFH-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
42+
; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; ZVFH-NEXT: vfredosum.vs v9, v8, v9, v0.t
@@ -67,7 +67,7 @@ declare half @llvm.vp.reduce.fadd.v4f16(half, <4 x half>, <4 x i1>, i32)
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define half @vpreduce_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fadd_v4f16:
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; ZVFH: # %bb.0:
70-
; ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
70+
; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; ZVFH-NEXT: vfredusum.vs v9, v8, v9, v0.t
@@ -93,7 +93,7 @@ define half @vpreduce_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroex
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define half @vpreduce_ord_fadd_v4f16(half %s, <4 x half> %v, <4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_ord_fadd_v4f16:
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; ZVFH: # %bb.0:
96-
; ZVFH-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
96+
; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; ZVFH-NEXT: vfredosum.vs v9, v8, v9, v0.t
@@ -121,7 +121,7 @@ declare float @llvm.vp.reduce.fadd.v2f32(float, <2 x float>, <2 x i1>, i32)
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define float @vpreduce_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fadd_v2f32:
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; CHECK: # %bb.0:
124-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
124+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
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; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t
@@ -134,7 +134,7 @@ define float @vpreduce_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 zer
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define float @vpreduce_ord_fadd_v2f32(float %s, <2 x float> %v, <2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_ord_fadd_v2f32:
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; CHECK: # %bb.0:
137-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
137+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
140140
; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t

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