Skip to content

Commit e13cbac

Browse files
AlexVlxAlexVlx
authored
[clang][CodeGen][SPIR-V] Fix incorrect SYCL usage, implement missing interface (#109415)
This is primarily meant to address the issue identified in #109182, around incorrect usage of `-fsycl-is-device`; we now have AMDGCN flavoured SPIR-V which retains the desired behaviour around the default AS and does not depend on the SYCL language being enabled to do so. Overall, there are three changes: 1. We unconditionally use the `SPIRDefIsGen` AS map for AMDGCNSPIRV target, as there is no case where the hack of setting default to private would be desirable, and it can be used for languages other than OCL/HIP; 2. We implement `SPIRVTargetCodeGenInfo::getGlobalVarAddressSpace` for SPIR-V in general, because otherwise using it from languages other than HIP or OpenCL would yield 0, incorrectly; 3. We remove the incorrect usage of `-fsycl-is-device`.
1 parent 9e65dca commit e13cbac

15 files changed

+106
-60
lines changed

‎clang/lib/Basic/Targets/SPIR.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -386,6 +386,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo final
386386
PointerWidth = PointerAlign = 64;
387387
SizeType = TargetInfo::UnsignedLong;
388388
PtrDiffType = IntPtrType = TargetInfo::SignedLong;
389+
AddrSpaceMap = &SPIRDefIsGenMap;
389390

390391
resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-"
391392
"v96:128-v192:256-v256:256-v512:512-v1024:1024-G1-P4-A0");
@@ -418,6 +419,10 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo final
418419

419420
void setAuxTarget(const TargetInfo *Aux) override;
420421

422+
void adjust(DiagnosticsEngine &Diags, LangOptions &Opts) override {
423+
TargetInfo::adjust(Diags, Opts);
424+
}
425+
421426
bool hasInt128Type() const override { return TargetInfo::hasInt128Type(); }
422427
};
423428

‎clang/lib/CodeGen/Targets/SPIR.cpp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,8 @@ class SPIRVTargetCodeGenInfo : public CommonSPIRTargetCodeGenInfo {
5858
SPIRVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT)
5959
: CommonSPIRTargetCodeGenInfo(std::make_unique<SPIRVABIInfo>(CGT)) {}
6060
void setCUDAKernelCallingConvention(const FunctionType *&FT) const override;
61+
LangAS getGlobalVarAddressSpace(CodeGenModule &CGM,
62+
const VarDecl *D) const override;
6163
llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions &LangOpts,
6264
SyncScope Scope,
6365
llvm::AtomicOrdering Ordering,
@@ -217,6 +219,28 @@ void SPIRVTargetCodeGenInfo::setCUDAKernelCallingConvention(
217219
}
218220
}
219221

222+
LangAS
223+
SPIRVTargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM,
224+
const VarDecl *D) const {
225+
assert(!CGM.getLangOpts().OpenCL &&
226+
!(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) &&
227+
"Address space agnostic languages only");
228+
// If we're here it means that we're using the SPIRDefIsGen ASMap, hence for
229+
// the global AS we can rely on either cuda_device or sycl_global to be
230+
// correct; however, since this is not a CUDA Device context, we use
231+
// sycl_global to prevent confusion with the assertion.
232+
LangAS DefaultGlobalAS = getLangASFromTargetAS(
233+
CGM.getContext().getTargetAddressSpace(LangAS::sycl_global));
234+
if (!D)
235+
return DefaultGlobalAS;
236+
237+
LangAS AddrSpace = D->getType().getAddressSpace();
238+
if (AddrSpace != LangAS::Default)
239+
return AddrSpace;
240+
241+
return DefaultGlobalAS;
242+
}
243+
220244
llvm::SyncScope::ID
221245
SPIRVTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &, SyncScope Scope,
222246
llvm::AtomicOrdering,

‎clang/test/CodeGenCXX/dynamic-cast-address-space.cpp

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --no-generate-body-for-unused-prefixes --version 4
22
// RUN: %clang_cc1 -I%S %s -triple amdgcn-amd-amdhsa -emit-llvm -fcxx-exceptions -fexceptions -o - | FileCheck %s
3-
// RUN: %clang_cc1 -I%S %s -triple spirv64-unknown-unknown -fsycl-is-device -emit-llvm -fcxx-exceptions -fexceptions -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
3+
// RUN: %clang_cc1 -I%S %s -triple spirv64-amd-amdhsa -emit-llvm -fcxx-exceptions -fexceptions -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
44

55
struct A { virtual void f(); };
66
struct B : A { };
@@ -15,7 +15,7 @@ B fail;
1515
// CHECK: @_ZTI1B = linkonce_odr addrspace(1) constant { ptr addrspace(1), ptr addrspace(1), ptr addrspace(1) } { ptr addrspace(1) getelementptr inbounds (ptr addrspace(1), ptr addrspace(1) @_ZTVN10__cxxabiv120__si_class_type_infoE, i64 2), ptr addrspace(1) @_ZTS1B, ptr addrspace(1) @_ZTI1A }, comdat, align 8
1616
// CHECK: @__oclc_ABI_version = weak_odr hidden local_unnamed_addr addrspace(4) constant i32 500
1717
//.
18-
// WITH-NONZERO-DEFAULT-AS: @_ZTV1B = linkonce_odr unnamed_addr addrspace(1) constant { [3 x ptr addrspace(1)] } { [3 x ptr addrspace(1)] [ptr addrspace(1) null, ptr addrspace(1) @_ZTI1B, ptr addrspace(1) addrspacecast (ptr @_ZN1A1fEv to ptr addrspace(1))] }, comdat, align 8
18+
// WITH-NONZERO-DEFAULT-AS: @_ZTV1B = linkonce_odr unnamed_addr addrspace(1) constant { [3 x ptr addrspace(1)] } { [3 x ptr addrspace(1)] [ptr addrspace(1) null, ptr addrspace(1) @_ZTI1B, ptr addrspace(1) addrspacecast (ptr addrspace(4) @_ZN1A1fEv to ptr addrspace(1))] }, comdat, align 8
1919
// WITH-NONZERO-DEFAULT-AS: @fail = addrspace(1) global { ptr addrspace(1) } { ptr addrspace(1) getelementptr inbounds inrange(-16, 8) ({ [3 x ptr addrspace(1)] }, ptr addrspace(1) @_ZTV1B, i32 0, i32 0, i32 2) }, align 8
2020
// WITH-NONZERO-DEFAULT-AS: @_ZTI1A = external addrspace(1) constant ptr addrspace(1)
2121
// WITH-NONZERO-DEFAULT-AS: @_ZTVN10__cxxabiv120__si_class_type_infoE = external addrspace(1) global [0 x ptr addrspace(1)]
@@ -60,7 +60,7 @@ B fail;
6060
// CHECK-NEXT: ret ptr addrspacecast (ptr addrspace(1) @fail to ptr)
6161
//
6262
// WITH-NONZERO-DEFAULT-AS-LABEL: define spir_func noundef align 8 dereferenceable(8) ptr addrspace(4) @_Z1fP1A(
63-
// WITH-NONZERO-DEFAULT-AS-SAME: ptr addrspace(4) noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] personality ptr @__gxx_personality_v0 {
63+
// WITH-NONZERO-DEFAULT-AS-SAME: ptr addrspace(4) noundef [[A:%.*]]) addrspace(4) #[[ATTR0:[0-9]+]] personality ptr addrspace(4) @__gxx_personality_v0 {
6464
// WITH-NONZERO-DEFAULT-AS-NEXT: entry:
6565
// WITH-NONZERO-DEFAULT-AS-NEXT: [[RETVAL:%.*]] = alloca ptr addrspace(4), align 8
6666
// WITH-NONZERO-DEFAULT-AS-NEXT: [[A_ADDR:%.*]] = alloca ptr addrspace(4), align 8
@@ -70,11 +70,11 @@ B fail;
7070
// WITH-NONZERO-DEFAULT-AS-NEXT: [[A_ADDR_ASCAST:%.*]] = addrspacecast ptr [[A_ADDR]] to ptr addrspace(4)
7171
// WITH-NONZERO-DEFAULT-AS-NEXT: store ptr addrspace(4) [[A]], ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
7272
// WITH-NONZERO-DEFAULT-AS-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[A_ADDR_ASCAST]], align 8
73-
// WITH-NONZERO-DEFAULT-AS-NEXT: [[TMP1:%.*]] = call spir_func ptr addrspace(4) @__dynamic_cast(ptr addrspace(4) [[TMP0]], ptr addrspace(1) @_ZTI1A, ptr addrspace(1) @_ZTI1B, i64 0) #[[ATTR3:[0-9]+]]
73+
// WITH-NONZERO-DEFAULT-AS-NEXT: [[TMP1:%.*]] = call spir_func addrspace(4) ptr addrspace(4) @__dynamic_cast(ptr addrspace(4) [[TMP0]], ptr addrspace(1) @_ZTI1A, ptr addrspace(1) @_ZTI1B, i64 0) #[[ATTR3:[0-9]+]]
7474
// WITH-NONZERO-DEFAULT-AS-NEXT: [[TMP2:%.*]] = icmp eq ptr addrspace(4) [[TMP1]], null
7575
// WITH-NONZERO-DEFAULT-AS-NEXT: br i1 [[TMP2]], label [[DYNAMIC_CAST_BAD_CAST:%.*]], label [[DYNAMIC_CAST_END:%.*]]
7676
// WITH-NONZERO-DEFAULT-AS: dynamic_cast.bad_cast:
77-
// WITH-NONZERO-DEFAULT-AS-NEXT: invoke spir_func void @__cxa_bad_cast() #[[ATTR4:[0-9]+]]
77+
// WITH-NONZERO-DEFAULT-AS-NEXT: invoke spir_func addrspace(4) void @__cxa_bad_cast() #[[ATTR4:[0-9]+]]
7878
// WITH-NONZERO-DEFAULT-AS-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
7979
// WITH-NONZERO-DEFAULT-AS: invoke.cont:
8080
// WITH-NONZERO-DEFAULT-AS-NEXT: unreachable
@@ -90,8 +90,8 @@ B fail;
9090
// WITH-NONZERO-DEFAULT-AS-NEXT: br label [[CATCH:%.*]]
9191
// WITH-NONZERO-DEFAULT-AS: catch:
9292
// WITH-NONZERO-DEFAULT-AS-NEXT: [[EXN:%.*]] = load ptr addrspace(4), ptr [[EXN_SLOT]], align 8
93-
// WITH-NONZERO-DEFAULT-AS-NEXT: [[TMP6:%.*]] = call spir_func ptr addrspace(4) @__cxa_begin_catch(ptr addrspace(4) [[EXN]]) #[[ATTR3]]
94-
// WITH-NONZERO-DEFAULT-AS-NEXT: call spir_func void @__cxa_end_catch()
93+
// WITH-NONZERO-DEFAULT-AS-NEXT: [[TMP6:%.*]] = call spir_func addrspace(4) ptr addrspace(4) @__cxa_begin_catch(ptr addrspace(4) [[EXN]]) #[[ATTR3]]
94+
// WITH-NONZERO-DEFAULT-AS-NEXT: call spir_func addrspace(4) void @__cxa_end_catch()
9595
// WITH-NONZERO-DEFAULT-AS-NEXT: br label [[TRY_CONT]]
9696
// WITH-NONZERO-DEFAULT-AS: try.cont:
9797
// WITH-NONZERO-DEFAULT-AS-NEXT: ret ptr addrspace(4) addrspacecast (ptr addrspace(1) @fail to ptr addrspace(4))
@@ -112,16 +112,17 @@ const B& f(A *a) {
112112
// CHECK: attributes #[[ATTR3]] = { nounwind }
113113
// CHECK: attributes #[[ATTR4]] = { noreturn }
114114
//.
115-
// WITH-NONZERO-DEFAULT-AS: attributes #[[ATTR0]] = { convergent mustprogress noinline norecurse nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
115+
// WITH-NONZERO-DEFAULT-AS: attributes #[[ATTR0]] = { mustprogress noinline optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot11-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+fp8-conversion-insts,+fp8-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx8-insts,+gfx9-insts,+gfx90a-insts,+gfx940-insts,+gws,+image-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32,+wavefrontsize64" }
116116
// WITH-NONZERO-DEFAULT-AS: attributes #[[ATTR1:[0-9]+]] = { nounwind willreturn memory(read) }
117-
// WITH-NONZERO-DEFAULT-AS: attributes #[[ATTR2:[0-9]+]] = { convergent nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
117+
// WITH-NONZERO-DEFAULT-AS: attributes #[[ATTR2:[0-9]+]] = { "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot11-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+fp8-conversion-insts,+fp8-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx8-insts,+gfx9-insts,+gfx90a-insts,+gfx940-insts,+gws,+image-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize32,+wavefrontsize64" }
118118
// WITH-NONZERO-DEFAULT-AS: attributes #[[ATTR3]] = { nounwind }
119119
// WITH-NONZERO-DEFAULT-AS: attributes #[[ATTR4]] = { noreturn }
120120
//.
121121
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
122122
// CHECK: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
123123
// CHECK: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
124124
//.
125-
// WITH-NONZERO-DEFAULT-AS: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
126-
// WITH-NONZERO-DEFAULT-AS: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
125+
// WITH-NONZERO-DEFAULT-AS: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
126+
// WITH-NONZERO-DEFAULT-AS: [[META1:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
127+
// WITH-NONZERO-DEFAULT-AS: [[META2:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
127128
//.

‎clang/test/CodeGenCXX/spirv-amdgcn-float16.cpp

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -7,22 +7,25 @@
77
// CHECK-NEXT: [[X:%.*]] = alloca half, align 2
88
// CHECK-NEXT: [[Y:%.*]] = alloca half, align 2
99
// CHECK-NEXT: [[Z:%.*]] = alloca half, align 2
10-
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr [[X]], align 2
11-
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr [[Y]], align 2
10+
// CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast ptr [[X]] to ptr addrspace(4)
11+
// CHECK-NEXT: [[Y_ASCAST:%.*]] = addrspacecast ptr [[Y]] to ptr addrspace(4)
12+
// CHECK-NEXT: [[Z_ASCAST:%.*]] = addrspacecast ptr [[Z]] to ptr addrspace(4)
13+
// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr addrspace(4) [[X_ASCAST]], align 2
14+
// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr addrspace(4) [[Y_ASCAST]], align 2
1215
// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
13-
// CHECK-NEXT: store half [[ADD]], ptr [[Z]], align 2
14-
// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr [[X]], align 2
15-
// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr [[Y]], align 2
16+
// CHECK-NEXT: store half [[ADD]], ptr addrspace(4) [[Z_ASCAST]], align 2
17+
// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr addrspace(4) [[X_ASCAST]], align 2
18+
// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr addrspace(4) [[Y_ASCAST]], align 2
1619
// CHECK-NEXT: [[SUB:%.*]] = fsub half [[TMP2]], [[TMP3]]
17-
// CHECK-NEXT: store half [[SUB]], ptr [[Z]], align 2
18-
// CHECK-NEXT: [[TMP4:%.*]] = load half, ptr [[X]], align 2
19-
// CHECK-NEXT: [[TMP5:%.*]] = load half, ptr [[Y]], align 2
20+
// CHECK-NEXT: store half [[SUB]], ptr addrspace(4) [[Z_ASCAST]], align 2
21+
// CHECK-NEXT: [[TMP4:%.*]] = load half, ptr addrspace(4) [[X_ASCAST]], align 2
22+
// CHECK-NEXT: [[TMP5:%.*]] = load half, ptr addrspace(4) [[Y_ASCAST]], align 2
2023
// CHECK-NEXT: [[MUL:%.*]] = fmul half [[TMP4]], [[TMP5]]
21-
// CHECK-NEXT: store half [[MUL]], ptr [[Z]], align 2
22-
// CHECK-NEXT: [[TMP6:%.*]] = load half, ptr [[X]], align 2
23-
// CHECK-NEXT: [[TMP7:%.*]] = load half, ptr [[Y]], align 2
24+
// CHECK-NEXT: store half [[MUL]], ptr addrspace(4) [[Z_ASCAST]], align 2
25+
// CHECK-NEXT: [[TMP6:%.*]] = load half, ptr addrspace(4) [[X_ASCAST]], align 2
26+
// CHECK-NEXT: [[TMP7:%.*]] = load half, ptr addrspace(4) [[Y_ASCAST]], align 2
2427
// CHECK-NEXT: [[DIV:%.*]] = fdiv half [[TMP6]], [[TMP7]]
25-
// CHECK-NEXT: store half [[DIV]], ptr [[Z]], align 2
28+
// CHECK-NEXT: store half [[DIV]], ptr addrspace(4) [[Z_ASCAST]], align 2
2629
// CHECK-NEXT: ret void
2730
//
2831
void f() {

‎clang/test/CodeGenCXX/template-param-objects-address-space.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -std=c++20 %s -emit-llvm -o - | FileCheck %s
2-
// RUN: %clang_cc1 -triple spirv64-unknown-unknown -fsycl-is-device -std=c++20 %s -emit-llvm -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
2+
// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -std=c++20 %s -emit-llvm -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
33

44
struct S { char buf[32]; };
55
template<S s> constexpr const char *begin() { return s.buf; }
@@ -37,6 +37,6 @@ const void *s = observable_addr<S{"hello world"}>();
3737
// CHECK: define linkonce_odr noundef ptr @_Z15observable_addrIXtl1StlA32_cLc104ELc101ELc108ELc108ELc111ELc32ELc119ELc111ELc114ELc108ELc100EEEEEPKvv()
3838
// WITH-NONZERO-DEFAULT-AS: define linkonce_odr {{.*}} noundef ptr addrspace(4) @_Z15observable_addrIXtl1StlA32_cLc104ELc101ELc108ELc108ELc111ELc32ELc119ELc111ELc114ELc108ELc100EEEEEPKvv()
3939
// CHECK: %call = call noundef ptr @_Z6calleePK1S(ptr noundef addrspacecast (ptr addrspace(1) [[HELLO]] to ptr))
40-
// WITH-NONZERO-DEFAULT-AS: %call = call {{.*}} noundef ptr addrspace(4) @_Z6calleePK1S(ptr addrspace(4) noundef addrspacecast (ptr addrspace(1) [[HELLO]] to ptr addrspace(4)))
40+
// WITH-NONZERO-DEFAULT-AS: %call = call {{.*}} noundef{{.*}} ptr addrspace(4) @_Z6calleePK1S(ptr addrspace(4) noundef addrspacecast (ptr addrspace(1) [[HELLO]] to ptr addrspace(4)))
4141
// CHECK: declare noundef ptr @_Z6calleePK1S(ptr noundef)
4242
// WITH-NONZERO-DEFAULT-AS: declare {{.*}} noundef ptr addrspace(4) @_Z6calleePK1S(ptr addrspace(4) noundef)

‎clang/test/CodeGenCXX/throw-expression-typeinfo-in-address-space.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: %clang_cc1 %s -triple amdgcn-amd-amdhsa -emit-llvm -fcxx-exceptions -fexceptions -std=c++11 -o - | FileCheck %s
2-
// RUN: %clang_cc1 %s -triple spirv64-unknown-unknown -fsycl-is-device -emit-llvm -fcxx-exceptions -fexceptions -std=c++11 -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
2+
// RUN: %clang_cc1 %s -triple spirv64-amd-amdhsa -emit-llvm -fcxx-exceptions -fexceptions -std=c++11 -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
33

44
struct X {
55
~X();

‎clang/test/CodeGenCXX/try-catch-with-address-space.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: %clang_cc1 %s -triple=amdgcn-amd-amdhsa -emit-llvm -o - -fcxx-exceptions -fexceptions | FileCheck %s
2-
// RUN: %clang_cc1 %s -triple=spirv64-unknown-unknown -fsycl-is-device -emit-llvm -o - -fcxx-exceptions -fexceptions | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
2+
// RUN: %clang_cc1 %s -triple=spirv64-amd-amdhsa -emit-llvm -o - -fcxx-exceptions -fexceptions | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
33

44
struct X { };
55

@@ -12,7 +12,7 @@ void f() {
1212
} catch (const X x) {
1313
// CHECK: catch ptr addrspace(1) @_ZTI1X
1414
// CHECK: call i32 @llvm.eh.typeid.for.p0(ptr addrspacecast (ptr addrspace(1) @_ZTI1X to ptr))
15-
// WITH-NONZERO-DEFAULT-AS: call i32 @llvm.eh.typeid.for.p4(ptr addrspace(4) addrspacecast (ptr addrspace(1) @_ZTI1X to ptr addrspace(4)))
15+
// WITH-NONZERO-DEFAULT-AS: call{{.*}} i32 @llvm.eh.typeid.for.p4(ptr addrspace(4) addrspacecast (ptr addrspace(1) @_ZTI1X to ptr addrspace(4)))
1616
}
1717
}
1818

@@ -23,6 +23,6 @@ void h() {
2323
} catch (char const(&)[4]) {
2424
// CHECK: catch ptr addrspace(1) @_ZTIA4_c
2525
// CHECK: call i32 @llvm.eh.typeid.for.p0(ptr addrspacecast (ptr addrspace(1) @_ZTIA4_c to ptr))
26-
// WITH-NONZERO-DEFAULT-AS: call i32 @llvm.eh.typeid.for.p4(ptr addrspace(4) addrspacecast (ptr addrspace(1) @_ZTIA4_c to ptr addrspace(4)))
26+
// WITH-NONZERO-DEFAULT-AS: call{{.*}} i32 @llvm.eh.typeid.for.p4(ptr addrspace(4) addrspacecast (ptr addrspace(1) @_ZTIA4_c to ptr addrspace(4)))
2727
}
2828
}

‎clang/test/CodeGenCXX/typeid-cxx11-with-address-space.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: %clang_cc1 -I%S %s -triple amdgcn-amd-amdhsa -emit-llvm -std=c++11 -o - | FileCheck %s
2-
// RUN: %clang_cc1 -I%S %s -triple spirv64-unknown-unknown -fsycl-is-device -emit-llvm -std=c++11 -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
2+
// RUN: %clang_cc1 -I%S %s -triple spirv64-amd-amdhsa -emit-llvm -std=c++11 -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
33
#include <typeinfo>
44

55
namespace Test1 {

‎clang/test/CodeGenCXX/typeid-with-address-space.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: %clang_cc1 -I%S %s -triple amdgcn-amd-amdhsa -emit-llvm -fcxx-exceptions -fexceptions -o - | FileCheck %s
2-
// RUN: %clang_cc1 -I%S %s -triple spirv64-unknown-unknown -fsycl-is-device -emit-llvm -fcxx-exceptions -fexceptions -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
2+
// RUN: %clang_cc1 -I%S %s -triple spirv64-amd-amdhsa -emit-llvm -fcxx-exceptions -fexceptions -o - | FileCheck %s --check-prefix=WITH-NONZERO-DEFAULT-AS
33
#include <typeinfo>
44

55
namespace Test1 {
@@ -39,7 +39,7 @@ const std::type_info &A10_c_ti = typeid(char const[10]);
3939
// CHECK-LABEL: define{{.*}} ptr @_ZN5Test11fEv
4040
// CHECK-SAME: personality ptr @__gxx_personality_v0
4141
// WITH-NONZERO-DEFAULT-AS-LABEL: define{{.*}} ptr addrspace(4) @_ZN5Test11fEv
42-
// WITH-NONZERO-DEFAULT-AS-SAME: personality ptr @__gxx_personality_v0
42+
// WITH-NONZERO-DEFAULT-AS-SAME: personality ptr addrspace(4) @__gxx_personality_v0
4343
const char *f() {
4444
try {
4545
// CHECK: br i1

0 commit comments

Comments
 (0)