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[X86] prefetch.ll - cleanup check prefixes identified in #92248
Avoid using leading numbers in check prefixes - replace with actual triple config names (and makes it easier to add X64 test coverage in a future commit).
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‎llvm/test/CodeGen/X86/prefetch.ll

Lines changed: 69 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,16 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=i686-- -mattr=+sse | FileCheck %s --check-prefix=SSE
3-
; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefix=SSE
4-
; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prfchw | FileCheck %s -check-prefix=PRFCHWSSE
5-
; RUN: llc < %s -mtriple=i686-- -mattr=+prfchw | FileCheck %s -check-prefix=PRFCHWSSE
6-
; RUN: llc < %s -mtriple=i686-- -mcpu=slm | FileCheck %s -check-prefix=PRFCHWSSE
7-
; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 | FileCheck %s -check-prefix=PRFCHWSSE
8-
; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 -mattr=-prfchw | FileCheck %s -check-prefix=SSE
9-
; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
10-
; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
11-
; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+3dnow,+prefetchwt1 | FileCheck %s -check-prefix=PREFETCHWT1
12-
; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow | FileCheck %s -check-prefix=3DNOW
13-
; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow,+prfchw | FileCheck %s -check-prefix=3DNOW
2+
; RUN: llc < %s -mtriple=i686-- -mattr=+sse | FileCheck %s --check-prefix=X86-SSE
3+
; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefix=X86-SSE
4+
; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prfchw | FileCheck %s -check-prefix=X86-PRFCHWSSE
5+
; RUN: llc < %s -mtriple=i686-- -mattr=+prfchw | FileCheck %s -check-prefix=X86-PRFCHWSSE
6+
; RUN: llc < %s -mtriple=i686-- -mcpu=slm | FileCheck %s -check-prefix=X86-PRFCHWSSE
7+
; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 | FileCheck %s -check-prefix=X86-PRFCHWSSE
8+
; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 -mattr=-prfchw | FileCheck %s -check-prefix=X86-SSE
9+
; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prefetchwt1 | FileCheck %s -check-prefix=X86-PREFETCHWT1
10+
; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+prefetchwt1 | FileCheck %s -check-prefix=X86-PREFETCHWT1
11+
; RUN: llc < %s -mtriple=i686-- -mattr=-sse,+3dnow,+prefetchwt1 | FileCheck %s -check-prefix=X86-PREFETCHWT1
12+
; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow | FileCheck %s -check-prefix=X86-3DNOW
13+
; RUN: llc < %s -mtriple=i686-- -mattr=+3dnow,+prfchw | FileCheck %s -check-prefix=X86-3DNOW
1414

1515
; Rules:
1616
; 3dnow by itself get you just the single prefetch instruction with no hints
@@ -22,67 +22,67 @@
2222
; rdar://10538297
2323

2424
define void @t(ptr %ptr) nounwind {
25-
; SSE-LABEL: t:
26-
; SSE: # %bb.0: # %entry
27-
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
28-
; SSE-NEXT: prefetcht2 (%eax)
29-
; SSE-NEXT: prefetcht1 (%eax)
30-
; SSE-NEXT: prefetcht0 (%eax)
31-
; SSE-NEXT: prefetchnta (%eax)
32-
; SSE-NEXT: prefetcht2 (%eax)
33-
; SSE-NEXT: prefetcht1 (%eax)
34-
; SSE-NEXT: prefetcht0 (%eax)
35-
; SSE-NEXT: prefetchnta (%eax)
36-
; SSE-NEXT: retl
25+
; X86-SSE-LABEL: t:
26+
; X86-SSE: # %bb.0: # %entry
27+
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
28+
; X86-SSE-NEXT: prefetcht2 (%eax)
29+
; X86-SSE-NEXT: prefetcht1 (%eax)
30+
; X86-SSE-NEXT: prefetcht0 (%eax)
31+
; X86-SSE-NEXT: prefetchnta (%eax)
32+
; X86-SSE-NEXT: prefetcht2 (%eax)
33+
; X86-SSE-NEXT: prefetcht1 (%eax)
34+
; X86-SSE-NEXT: prefetcht0 (%eax)
35+
; X86-SSE-NEXT: prefetchnta (%eax)
36+
; X86-SSE-NEXT: retl
3737
;
38-
; PRFCHWSSE-LABEL: t:
39-
; PRFCHWSSE: # %bb.0: # %entry
40-
; PRFCHWSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
41-
; PRFCHWSSE-NEXT: prefetcht2 (%eax)
42-
; PRFCHWSSE-NEXT: prefetcht1 (%eax)
43-
; PRFCHWSSE-NEXT: prefetcht0 (%eax)
44-
; PRFCHWSSE-NEXT: prefetchnta (%eax)
45-
; PRFCHWSSE-NEXT: prefetchw (%eax)
46-
; PRFCHWSSE-NEXT: prefetchw (%eax)
47-
; PRFCHWSSE-NEXT: prefetchw (%eax)
48-
; PRFCHWSSE-NEXT: prefetchw (%eax)
49-
; PRFCHWSSE-NEXT: retl
38+
; X86-PRFCHWSSE-LABEL: t:
39+
; X86-PRFCHWSSE: # %bb.0: # %entry
40+
; X86-PRFCHWSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
41+
; X86-PRFCHWSSE-NEXT: prefetcht2 (%eax)
42+
; X86-PRFCHWSSE-NEXT: prefetcht1 (%eax)
43+
; X86-PRFCHWSSE-NEXT: prefetcht0 (%eax)
44+
; X86-PRFCHWSSE-NEXT: prefetchnta (%eax)
45+
; X86-PRFCHWSSE-NEXT: prefetchw (%eax)
46+
; X86-PRFCHWSSE-NEXT: prefetchw (%eax)
47+
; X86-PRFCHWSSE-NEXT: prefetchw (%eax)
48+
; X86-PRFCHWSSE-NEXT: prefetchw (%eax)
49+
; X86-PRFCHWSSE-NEXT: retl
5050
;
51-
; PREFETCHWT1-LABEL: t:
52-
; PREFETCHWT1: # %bb.0: # %entry
53-
; PREFETCHWT1-NEXT: movl {{[0-9]+}}(%esp), %eax
54-
; PREFETCHWT1-NEXT: prefetcht2 (%eax)
55-
; PREFETCHWT1-NEXT: prefetcht1 (%eax)
56-
; PREFETCHWT1-NEXT: prefetcht0 (%eax)
57-
; PREFETCHWT1-NEXT: prefetchnta (%eax)
58-
; PREFETCHWT1-NEXT: prefetchwt1 (%eax)
59-
; PREFETCHWT1-NEXT: prefetchwt1 (%eax)
60-
; PREFETCHWT1-NEXT: prefetchw (%eax)
61-
; PREFETCHWT1-NEXT: prefetchwt1 (%eax)
62-
; PREFETCHWT1-NEXT: retl
51+
; X86-PREFETCHWT1-LABEL: t:
52+
; X86-PREFETCHWT1: # %bb.0: # %entry
53+
; X86-PREFETCHWT1-NEXT: movl {{[0-9]+}}(%esp), %eax
54+
; X86-PREFETCHWT1-NEXT: prefetcht2 (%eax)
55+
; X86-PREFETCHWT1-NEXT: prefetcht1 (%eax)
56+
; X86-PREFETCHWT1-NEXT: prefetcht0 (%eax)
57+
; X86-PREFETCHWT1-NEXT: prefetchnta (%eax)
58+
; X86-PREFETCHWT1-NEXT: prefetchwt1 (%eax)
59+
; X86-PREFETCHWT1-NEXT: prefetchwt1 (%eax)
60+
; X86-PREFETCHWT1-NEXT: prefetchw (%eax)
61+
; X86-PREFETCHWT1-NEXT: prefetchwt1 (%eax)
62+
; X86-PREFETCHWT1-NEXT: retl
6363
;
64-
; 3DNOW-LABEL: t:
65-
; 3DNOW: # %bb.0: # %entry
66-
; 3DNOW-NEXT: movl {{[0-9]+}}(%esp), %eax
67-
; 3DNOW-NEXT: prefetch (%eax)
68-
; 3DNOW-NEXT: prefetch (%eax)
69-
; 3DNOW-NEXT: prefetch (%eax)
70-
; 3DNOW-NEXT: prefetch (%eax)
71-
; 3DNOW-NEXT: prefetchw (%eax)
72-
; 3DNOW-NEXT: prefetchw (%eax)
73-
; 3DNOW-NEXT: prefetchw (%eax)
74-
; 3DNOW-NEXT: prefetchw (%eax)
75-
; 3DNOW-NEXT: retl
64+
; X86-3DNOW-LABEL: t:
65+
; X86-3DNOW: # %bb.0: # %entry
66+
; X86-3DNOW-NEXT: movl {{[0-9]+}}(%esp), %eax
67+
; X86-3DNOW-NEXT: prefetch (%eax)
68+
; X86-3DNOW-NEXT: prefetch (%eax)
69+
; X86-3DNOW-NEXT: prefetch (%eax)
70+
; X86-3DNOW-NEXT: prefetch (%eax)
71+
; X86-3DNOW-NEXT: prefetchw (%eax)
72+
; X86-3DNOW-NEXT: prefetchw (%eax)
73+
; X86-3DNOW-NEXT: prefetchw (%eax)
74+
; X86-3DNOW-NEXT: prefetchw (%eax)
75+
; X86-3DNOW-NEXT: retl
7676
entry:
77-
tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 1, i32 1 )
78-
tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 2, i32 1 )
79-
tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 1 )
80-
tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 0, i32 1 )
81-
tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 1, i32 1 )
82-
tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 2, i32 1 )
83-
tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 3, i32 1 )
84-
tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 0, i32 1 )
85-
ret void
77+
tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 1, i32 1 )
78+
tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 2, i32 1 )
79+
tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 1 )
80+
tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 0, i32 1 )
81+
tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 1, i32 1 )
82+
tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 2, i32 1 )
83+
tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 3, i32 1 )
84+
tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 0, i32 1 )
85+
ret void
8686
}
8787

8888
declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind

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