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[InstCombine] Pre-commit tests (NFC)
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  • llvm/test/Transforms/InstCombine

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llvm/test/Transforms/InstCombine/lshr.ll

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@@ -360,8 +360,65 @@ define <3 x i14> @mul_splat_fold_vec(<3 x i14> %x) {
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ret <3 x i14> %t
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}
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define i32 @mul_times_3_div_2 (i32 %x) {
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; CHECK-LABEL: @mul_times_3_div_2(
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; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[X:%.*]], 3
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 1
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%2 = mul nsw nuw i32 %x, 3
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%3 = lshr i32 %2, 1
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ret i32 %3
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}
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define i32 @shl_add_lshr (i32 %x, i32 %c, i32 %y) {
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; CHECK-LABEL: @shl_add_lshr(
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; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 [[X:%.*]], [[C:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], [[Y:%.*]]
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; CHECK-NEXT: [[TMP3:%.*]] = lshr exact i32 [[TMP2]], [[C]]
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%2 = shl nuw i32 %x, %c
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%3 = add nsw nuw i32 %2, %y
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%4 = lshr exact i32 %3, %c
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ret i32 %4
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}
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define i32 @ashr_mul_times_3_div_2 (i32 %0) {
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; CHECK-LABEL: @ashr_mul_times_3_div_2(
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; CHECK-NEXT: [[TMP2:%.*]] = mul nuw nsw i32 [[TMP0:%.*]], 3
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; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP2]], 1
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%2 = mul nsw nuw i32 %0, 3
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%3 = ashr i32 %2, 1
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ret i32 %3
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}
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define i32 @ashr_mul_times_3_div_2_exact (i32 %0) {
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; CHECK-LABEL: @ashr_mul_times_3_div_2_exact(
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; CHECK-NEXT: [[TMP2:%.*]] = mul nsw i32 [[TMP0:%.*]], 3
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; CHECK-NEXT: [[TMP3:%.*]] = ashr exact i32 [[TMP2]], 1
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%2 = mul nsw i32 %0, 3
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%3 = ashr exact i32 %2, 1
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ret i32 %3
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}
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; Negative test
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define i32 @mul_times_3_div_2_no_nsw (i32 %x) {
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; CHECK-LABEL: @mul_times_3_div_2_no_nsw(
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[X:%.*]], 3
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 1
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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%2 = mul i32 %x, 3
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%3 = lshr i32 %2, 1
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ret i32 %3
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}
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define i32 @mul_splat_fold_wrong_mul_const(i32 %x) {
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; CHECK-LABEL: @mul_splat_fold_wrong_mul_const(
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; CHECK-NEXT: [[M:%.*]] = mul nuw i32 [[X:%.*]], 65538

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