Meet review items

Author: AlexeyMerzlyakov

lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py

@@ -21,8 +21,8 @@ class LinuxCoreTestCase(TestBase):
     _x86_64_pid = 32259
     _s390x_pid = 1045
     _ppc64le_pid = 28147
-    _riscv64_pid = 89328
-    _riscv64_no_fpr_pid = 97
+    _riscv64_gpr_fpr_pid = 1089
+    _riscv64_gpr_only_pid = 97
 
     _aarch64_regions = 4
     _i386_regions = 4
@@ -62,17 +62,21 @@ def test_s390x(self):
         self.do_test("linux-s390x", self._s390x_pid, self._s390x_regions, "a.out")
 
     @skipIfLLVMTargetMissing("RISCV")
-    def test_riscv64(self):
+    def test_riscv64_gpr_fpr(self):
         """Test that lldb can read the process information from an riscv64 linux core file."""
-        self.do_test("linux-riscv64", self._riscv64_pid, self._riscv64_regions, "a.out")
+        self.do_test(
+            "linux-riscv64.gpr_fpr",
+            self._riscv64_gpr_fpr_pid,
+            self._riscv64_regions,
+            "a.out")
 
     @skipIfLLVMTargetMissing("RISCV")
-    def test_riscv64_no_fpr(self):
+    def test_riscv64_gpr_only(self):
         """Test that lldb can read the process information from an riscv64 linux core file
         made for a RV64IMAC target, having no FP-registers."""
         self.do_test(
-            "linux-riscv64.no_fpr",
-            self._riscv64_no_fpr_pid,
+            "linux-riscv64.gpr_only",
+            self._riscv64_gpr_only_pid,
             self._riscv64_regions,
             "a.out",
         )
@@ -680,46 +684,47 @@ def test_arm_core(self):
         self.expect("register read --all")
 
     @skipIfLLVMTargetMissing("RISCV")
-    def test_riscv64_regs(self):
+    def test_riscv64_regs_gpr_fpr(self):
         # check basic registers using 64 bit RISC-V core file
         target = self.dbg.CreateTarget(None)
         self.assertTrue(target, VALID_TARGET)
-        process = target.LoadCore("linux-riscv64.core")
+        process = target.LoadCore("linux-riscv64.gpr_fpr.core")
 
         values = {}
-        values["pc"] = "0x000000000001015e"
-        values["ra"] = "0x000000000001018c"
-        values["sp"] = "0x0000003fffd132a0"
-        values["gp"] = "0x0000002ae919af50"
-        values["tp"] = "0x0000003fdceae3e0"
-        values["t0"] = "0x0"
-        values["t1"] = "0x0000002ae9187b1c"
-        values["t2"] = "0x0000000000000021"
-        values["fp"] = "0x0000003fffd132d0"
-        values["s1"] = "0x0000002ae919cd98"
+        values["pc"] = "0x000000000001016e"
+        values["ra"] = "0x00000000000101a4"
+        values["sp"] = "0x0000003fffc1d2d0"
+        values["gp"] = "0x0000002ae6eccf50"
+        values["tp"] = "0x0000003ff3cb5400"
+        values["t0"] = "0x7f7f7f7fffffffff"
+        values["t1"] = "0x0000002ae6eb9b1c"
+        values["t2"] = "0xffffffffffffffff"
+        values["fp"] = "0x0000003fffc1d300"
+        values["s1"] = "0x0000002ae6eced98"
         values["a0"] = "0x0"
         values["a1"] = "0x0000000000010144"
-        values["a2"] = "0x0000002ae919cdb0"
-        values["a3"] = "0x000000000000002f"
-        values["a4"] = "0x000000000000002f"
+        values["a2"] = "0x0000002ae6ecedb0"
+        values["a3"] = "0xafdbdbff81cf7f81"
+        values["a4"] = "0x00000000000101e4"
         values["a5"] = "0x0"
-        values["a6"] = "0x7efefefefefefeff"
+        values["a6"] = "0x2f5b5a40014e0001"
         values["a7"] = "0x00000000000000dd"
-        values["s2"] = "0x0000002ae9196860"
-        values["s3"] = "0x0000002ae919cdb0"
-        values["s4"] = "0x0000003fffc63be8"
-        values["s5"] = "0x0000002ae919cb78"
-        values["s6"] = "0x0000002ae9196860"
-        values["s7"] = "0x0000002ae9196860"
+        values["s2"] = "0x0000002ae6ec8860"
+        values["s3"] = "0x0000002ae6ecedb0"
+        values["s4"] = "0x0000003fff886c18"
+        values["s5"] = "0x0000002ae6eceb78"
+        values["s6"] = "0x0000002ae6ec8860"
+        values["s7"] = "0x0000002ae6ec8860"
         values["s8"] = "0x0"
         values["s9"] = "0x000000000000000f"
-        values["s10"] = "0x0000002ae919a8d0"
+        values["s10"] = "0x0000002ae6ecc8d0"
         values["s11"] = "0x0000000000000008"
-        values["t3"] = "0x0000003fdce07df4"
+        values["t3"] = "0x0000003ff3be3728"
         values["t4"] = "0x0"
-        values["t5"] = "0x0000000000000020"
-        values["t6"] = "0x0000002ae919f1b0"
+        values["t5"] = "0x0000000000000002"
+        values["t6"] = "0x0000002ae6ed08b9"
         values["zero"] = "0x0"
+        values["fa5"] = "0xffffffff423c0000"
         values["fcsr"] = "0x00000000"
 
         fpr_names = {
@@ -740,7 +745,6 @@ def test_riscv64_regs(self):
             "fa2",
             "fa3",
             "fa4",
-            "fa5",
             "fa6",
             "fa7",
             "fs0",
@@ -773,11 +777,11 @@ def test_riscv64_regs(self):
         self.expect("register read --all")
 
     @skipIfLLVMTargetMissing("RISCV")
-    def test_riscv64_no_fpr_regs(self):
+    def test_riscv64_regs_gpr_only(self):
         # check registers using 64 bit RISC-V core file containing GP-registers only
         target = self.dbg.CreateTarget(None)
         self.assertTrue(target, VALID_TARGET)
-        process = target.LoadCore("linux-riscv64.no_fpr.core")
+        process = target.LoadCore("linux-riscv64.gpr_only.core")
 
         values = {}
         values["pc"] = "0x0000000000010164"