Skip to content

Commit e85bfa6

Browse files
jthackrayjthackray
authored
[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs (#85401)
[AArch64] Add support for Cortex-A520AE and Cortex-A720AE CPUs Cortex-A520AE and Cortex-A720AE are Armv9.2 AArch64 CPUs. Technical Reference Manual for Cortex-A520AE: https://developer.arm.com/documentation/107726/latest/ Technical Reference Manual for Cortex-A720AE: https://developer.arm.com/documentation/102828/latest/
1 parent a4b2363 commit e85bfa6

File tree

8 files changed

+84
-3
lines changed

8 files changed

+84
-3
lines changed

‎clang/docs/ReleaseNotes.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -445,6 +445,8 @@ Arm and AArch64 Support
445445
like ``target_version`` or ``target_clones``.
446446
- Support has been added for the following processors (-mcpu identifiers in parenthesis):
447447
* Arm Cortex-A78AE (cortex-a78ae).
448+
* Arm Cortex-A520AE (cortex-a520ae).
449+
* Arm Cortex-A720AE (cortex-a720ae).
448450

449451
Android Support
450452
^^^^^^^^^^^^^^^

‎clang/test/Driver/aarch64-mcpu.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,8 @@
5656
// CORTEX-A715: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a715"
5757
// RUN: %clang --target=aarch64 -mcpu=cortex-a720 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A720 %s
5858
// CORTEX-A720: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a720"
59+
// RUN: %clang --target=aarch64 -mcpu=cortex-a720ae -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A720AE %s
60+
// CORTEX-A720AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a720ae"
5961
// RUN: %clang --target=aarch64 -mcpu=neoverse-e1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-E1 %s
6062
// NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-e1"
6163
// RUN: %clang --target=aarch64 -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V1 %s
@@ -70,6 +72,8 @@
7072
// NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-512tvb"
7173
// RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A520 %s
7274
// CORTEX-A520: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a520"
75+
// RUN: %clang --target=aarch64 -mcpu=cortex-a520ae -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A520AE %s
76+
// CORTEX-A520AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a520ae"
7377

7478
// RUN: %clang --target=aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXR82 %s
7579
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"

‎clang/test/Misc/target-invalid-cpu-note.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55

66
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
77
// AARCH64: error: unknown target CPU 'not-a-cpu'
8-
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
8+
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
99

1010
// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
1111
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
12-
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
12+
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
1313

1414
// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
1515
// X86: error: unknown target CPU 'not-a-cpu'

‎llvm/docs/ReleaseNotes.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,8 @@ Changes to Interprocedural Optimizations
6767
Changes to the AArch64 Backend
6868
------------------------------
6969

70+
* Added support for Cortex-A78AE, Cortex-A520AE and Cortex-A720AE CPUs.
71+
7072
Changes to the AMDGPU Backend
7173
-----------------------------
7274

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -554,6 +554,11 @@ inline constexpr CpuInfo CpuInfos[] = {
554554
{AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE,
555555
AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
556556
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})},
557+
{"cortex-a520ae", ARMV9_2A,
558+
AArch64::ExtensionBitset(
559+
{AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_MTE,
560+
AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
561+
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, AArch64::AEK_PREDRES})},
557562
{"cortex-a57", ARMV8A,
558563
AArch64::ExtensionBitset(
559564
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_CRC})},
@@ -621,6 +626,12 @@ inline constexpr CpuInfo CpuInfos[] = {
621626
AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
622627
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
623628
AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
629+
{"cortex-a720ae", ARMV9_2A,
630+
AArch64::ExtensionBitset({AArch64::AEK_SB, AArch64::AEK_SSBS,
631+
AArch64::AEK_MTE, AArch64::AEK_FP16FML,
632+
AArch64::AEK_PAUTH, AArch64::AEK_SVE2BITPERM,
633+
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
634+
AArch64::AEK_PREDRES, AArch64::AEK_PROFILE})},
624635
{"cortex-r82", ARMV8R, AArch64::ExtensionBitset({AArch64::AEK_LSE})},
625636
{"cortex-x1", ARMV8_2A,
626637
AArch64::ExtensionBitset({AArch64::AEK_AES, AArch64::AEK_SHA2,

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -873,6 +873,12 @@ def TuneA520 : SubtargetFeature<"a520", "ARMProcFamily", "CortexA520",
873873
FeatureFuseAdrpAdd,
874874
FeaturePostRAScheduler]>;
875875

876+
def TuneA520AE : SubtargetFeature<"a520ae", "ARMProcFamily", "CortexA520",
877+
"Cortex-A520AE ARM processors", [
878+
FeatureFuseAES,
879+
FeatureFuseAdrpAdd,
880+
FeaturePostRAScheduler]>;
881+
876882
def TuneA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
877883
"Cortex-A57 ARM processors", [
878884
FeatureFuseAES,
@@ -1001,6 +1007,17 @@ def TuneA720 : SubtargetFeature<"a720", "ARMProcFamily", "CortexA720",
10011007
FeatureEnableSelectOptimize,
10021008
FeaturePredictableSelectIsExpensive]>;
10031009

1010+
def TuneA720AE : SubtargetFeature<"a720ae", "ARMProcFamily", "CortexA720",
1011+
"Cortex-A720AE ARM processors", [
1012+
FeatureFuseAES,
1013+
FeaturePostRAScheduler,
1014+
FeatureCmpBccFusion,
1015+
FeatureAddrLSLFast,
1016+
FeatureALULSLFast,
1017+
FeatureFuseAdrpAdd,
1018+
FeatureEnableSelectOptimize,
1019+
FeaturePredictableSelectIsExpensive]>;
1020+
10041021
def TuneR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
10051022
"CortexR82",
10061023
"Cortex-R82 ARM processors", [
@@ -1423,6 +1440,9 @@ def ProcessorFeatures {
14231440
list<SubtargetFeature> A520 = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
14241441
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
14251442
FeatureFP16FML];
1443+
list<SubtargetFeature> A520AE = [HasV9_2aOps, FeaturePerfMon, FeatureAM,
1444+
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
1445+
FeatureFP16FML];
14261446
list<SubtargetFeature> A65 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
14271447
FeatureNEON, FeatureFullFP16, FeatureDotProd,
14281448
FeatureRCPC, FeatureSSBS, FeatureRAS,
@@ -1456,6 +1476,9 @@ def ProcessorFeatures {
14561476
list<SubtargetFeature> A720 = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
14571477
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
14581478
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF];
1479+
list<SubtargetFeature> A720AE = [HasV9_2aOps, FeatureMTE, FeatureFP16FML,
1480+
FeatureTRBE, FeatureSVE2BitPerm, FeatureETE,
1481+
FeaturePerfMon, FeatureSPE, FeatureSPE_EEF];
14591482
list<SubtargetFeature> R82 = [HasV8_0rOps, FeaturePerfMon, FeatureFullFP16,
14601483
FeatureFP16FML, FeatureSSBS, FeaturePredRes,
14611484
FeatureSB, FeatureRDM, FeatureDotProd,
@@ -1598,6 +1621,8 @@ def : ProcessorModel<"cortex-a510", CortexA510Model, ProcessorFeatures.A510,
15981621
[TuneA510]>;
15991622
def : ProcessorModel<"cortex-a520", CortexA510Model, ProcessorFeatures.A520,
16001623
[TuneA520]>;
1624+
def : ProcessorModel<"cortex-a520ae", CortexA510Model, ProcessorFeatures.A520AE,
1625+
[TuneA520AE]>;
16011626
def : ProcessorModel<"cortex-a57", CortexA57Model, ProcessorFeatures.A53,
16021627
[TuneA57]>;
16031628
def : ProcessorModel<"cortex-a65", CortexA53Model, ProcessorFeatures.A65,
@@ -1628,6 +1653,8 @@ def : ProcessorModel<"cortex-a715", NeoverseN2Model, ProcessorFeatures.A715,
16281653
[TuneA715]>;
16291654
def : ProcessorModel<"cortex-a720", NeoverseN2Model, ProcessorFeatures.A720,
16301655
[TuneA720]>;
1656+
def : ProcessorModel<"cortex-a720ae", NeoverseN2Model, ProcessorFeatures.A720AE,
1657+
[TuneA720AE]>;
16311658
def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82,
16321659
[TuneR82]>;
16331660
def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1,

‎llvm/lib/TargetParser/Host.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -220,6 +220,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
220220
.Case("0xd05", "cortex-a55")
221221
.Case("0xd46", "cortex-a510")
222222
.Case("0xd80", "cortex-a520")
223+
.Case("0xd88", "cortex-a520ae")
223224
.Case("0xd07", "cortex-a57")
224225
.Case("0xd06", "cortex-a65")
225226
.Case("0xd43", "cortex-a65ae")
@@ -235,6 +236,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
235236
.Case("0xd47", "cortex-a710")
236237
.Case("0xd4d", "cortex-a715")
237238
.Case("0xd81", "cortex-a720")
239+
.Case("0xd89", "cortex-a720ae")
238240
.Case("0xd44", "cortex-x1")
239241
.Case("0xd4c", "cortex-x1c")
240242
.Case("0xd48", "cortex-x2")

‎llvm/unittests/TargetParser/TargetParserTest.cpp

Lines changed: 34 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1140,6 +1140,22 @@ INSTANTIATE_TEST_SUITE_P(
11401140
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
11411141
AArch64::AEK_JSCVT, AArch64::AEK_FCMA}),
11421142
"9.2-A"),
1143+
ARMCPUTestParams<AArch64::ExtensionBitset>(
1144+
"cortex-a520ae", "armv9.2-a", "crypto-neon-fp-armv8",
1145+
AArch64::ExtensionBitset(
1146+
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
1147+
AArch64::AEK_SVE, AArch64::AEK_SVE2,
1148+
AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
1149+
AArch64::AEK_LSE, AArch64::AEK_RDM,
1150+
AArch64::AEK_SIMD, AArch64::AEK_RCPC,
1151+
AArch64::AEK_RAS, AArch64::AEK_CRC,
1152+
AArch64::AEK_FP, AArch64::AEK_SB,
1153+
AArch64::AEK_SSBS, AArch64::AEK_MTE,
1154+
AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
1155+
AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
1156+
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
1157+
AArch64::AEK_JSCVT, AArch64::AEK_FCMA}),
1158+
"9.2-A"),
11431159
ARMCPUTestParams<AArch64::ExtensionBitset>(
11441160
"cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
11451161
AArch64::ExtensionBitset({AArch64::AEK_CRC, AArch64::AEK_AES,
@@ -1283,6 +1299,23 @@ INSTANTIATE_TEST_SUITE_P(
12831299
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
12841300
AArch64::AEK_FCMA}),
12851301
"9.2-A"),
1302+
ARMCPUTestParams<AArch64::ExtensionBitset>(
1303+
"cortex-a720ae", "armv9.2-a", "crypto-neon-fp-armv8",
1304+
AArch64::ExtensionBitset(
1305+
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
1306+
AArch64::AEK_SVE, AArch64::AEK_SVE2,
1307+
AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
1308+
AArch64::AEK_LSE, AArch64::AEK_RDM,
1309+
AArch64::AEK_SIMD, AArch64::AEK_RCPC,
1310+
AArch64::AEK_RAS, AArch64::AEK_CRC,
1311+
AArch64::AEK_FP, AArch64::AEK_SB,
1312+
AArch64::AEK_SSBS, AArch64::AEK_MTE,
1313+
AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
1314+
AArch64::AEK_SVE2BITPERM, AArch64::AEK_FLAGM,
1315+
AArch64::AEK_PERFMON, AArch64::AEK_PREDRES,
1316+
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
1317+
AArch64::AEK_FCMA}),
1318+
"9.2-A"),
12861319
ARMCPUTestParams<AArch64::ExtensionBitset>(
12871320
"neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
12881321
AArch64::ExtensionBitset(
@@ -1717,7 +1750,7 @@ INSTANTIATE_TEST_SUITE_P(
17171750
ARMCPUTestParams<AArch64::ExtensionBitset>::PrintToStringParamName);
17181751

17191752
// Note: number of CPUs includes aliases.
1720-
static constexpr unsigned NumAArch64CPUArchs = 70;
1753+
static constexpr unsigned NumAArch64CPUArchs = 72;
17211754

17221755
TEST(TargetParserTest, testAArch64CPUArchList) {
17231756
SmallVector<StringRef, NumAArch64CPUArchs> List;

0 commit comments

Comments
 (0)