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Use MachineInstr::substituteRegister
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+8
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llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 8 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -214,7 +214,6 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
214214
Reg1.isPhysical() ? MI.getOperand(Idx1).isRenamable() : false;
215215
bool Reg2IsRenamable =
216216
Reg2.isPhysical() ? MI.getOperand(Idx2).isRenamable() : false;
217-
218217
// If destination is tied to either of the commuted source register, then
219218
// it must be updated.
220219
if (HasDef && Reg0 == Reg1 &&
@@ -229,24 +228,6 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
229228
SubReg0 = SubReg1;
230229
}
231230

232-
// For a case like this:
233-
// %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
234-
// we need to update the implicit-def after commuting to result in:
235-
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
236-
SmallVector<unsigned> UpdateImplicitDefIdx;
237-
if (HasDef && MI.hasImplicitDef() && MI.getOperand(0).getReg() != Reg0) {
238-
const TargetRegisterInfo *TRI =
239-
MI.getMF()->getSubtarget().getRegisterInfo();
240-
Register OrigReg0 = MI.getOperand(0).getReg();
241-
for (auto [OpNo, MO] : llvm::enumerate(MI.implicit_operands())) {
242-
Register ImplReg = MO.getReg();
243-
if ((ImplReg.isVirtual() && ImplReg == OrigReg0) ||
244-
(ImplReg.isPhysical() && OrigReg0.isPhysical() &&
245-
TRI->isSubRegisterEq(ImplReg, OrigReg0)))
246-
UpdateImplicitDefIdx.push_back(OpNo + MI.getNumExplicitOperands());
247-
}
248-
}
249-
250231
MachineInstr *CommutedMI = nullptr;
251232
if (NewMI) {
252233
// Create a new instruction.
@@ -257,10 +238,15 @@ MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr &MI,
257238
}
258239

259240
if (HasDef) {
260-
CommutedMI->getOperand(0).setReg(Reg0);
241+
// Use `substituteRegister` so that for a case like this:
242+
// %0.sub = INST %0.sub(tied), %1.sub, implicit-def %0
243+
// the implicit-def is also updated, to result in:
244+
// %1.sub = INST %1.sub(tied), %0.sub, implicit-def %1
245+
const TargetRegisterInfo &TRI =
246+
*MI.getMF()->getSubtarget().getRegisterInfo();
247+
Register FromReg = CommutedMI->getOperand(0).getReg();
248+
CommutedMI->substituteRegister(FromReg, Reg0, /*SubRegIdx*/0, TRI);
261249
CommutedMI->getOperand(0).setSubReg(SubReg0);
262-
for (unsigned Idx : UpdateImplicitDefIdx)
263-
CommutedMI->getOperand(Idx).setReg(Reg0);
264250
}
265251
CommutedMI->getOperand(Idx2).setReg(Reg1);
266252
CommutedMI->getOperand(Idx1).setReg(Reg2);

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