@@ -52,7 +52,7 @@ define i16 @test_access_size_not_multiple_of_align(i64 %len, ptr %test_base) {
52
52
; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]]
53
53
; CHECK: scalar.ph:
54
54
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
55
- ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP18 ]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
55
+ ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP17 ]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
56
56
; CHECK-NEXT: br label [[LOOP:%.*]]
57
57
; CHECK: loop:
58
58
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
@@ -149,7 +149,7 @@ define i32 @test_access_size_multiple_of_align_but_offset_by_1(i64 %len, ptr %te
149
149
; CHECK-NEXT: br i1 true, label [[LOOP_EXIT:%.*]], label [[SCALAR_PH]]
150
150
; CHECK: scalar.ph:
151
151
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4096, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
152
- ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP18 ]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
152
+ ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP17 ]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
153
153
; CHECK-NEXT: br label [[LOOP:%.*]]
154
154
; CHECK: loop:
155
155
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
0 commit comments