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AMDGPU/GlobalISel: add RegBankLegalize rules for select
Uniform condition S1 is AnyExtended to S32 and high bits are cleaned using AND with 1. Divergent S1 uses VCC. Using B32/B64 rules to cover scalars vector and pointer types. Divergent B64 is split to S32.
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+654
-1280
lines changed

5 files changed

+654
-1280
lines changed

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
2222
#include "llvm/CodeGen/MachineUniformityAnalysis.h"
2323
#include "llvm/IR/IntrinsicsAMDGPU.h"
24+
#include "llvm/Support/AMDGPUAddrSpace.h"
2425

2526
#define DEBUG_TYPE "amdgpu-regbanklegalize"
2627

@@ -286,6 +287,22 @@ void RegBankLegalizeHelper::lowerSplitTo32(MachineInstr &MI) {
286287
MI.eraseFromParent();
287288
}
288289

290+
void RegBankLegalizeHelper::lowerSplitTo32Sel(MachineInstr &MI) {
291+
Register Dst = MI.getOperand(0).getReg();
292+
LLT Ty = MRI.getType(Dst) == V4S16 ? V2S16 : S32;
293+
auto Op2 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(2).getReg());
294+
auto Op3 = B.buildUnmerge({VgprRB, Ty}, MI.getOperand(3).getReg());
295+
Register Cond = MI.getOperand(1).getReg();
296+
auto Flags = MI.getFlags();
297+
auto Lo =
298+
B.buildSelect({VgprRB, Ty}, Cond, Op2.getReg(0), Op3.getReg(0), Flags);
299+
auto Hi =
300+
B.buildSelect({VgprRB, Ty}, Cond, Op2.getReg(1), Op3.getReg(1), Flags);
301+
302+
B.buildMergeLikeInstr(Dst, {Lo, Hi});
303+
MI.eraseFromParent();
304+
}
305+
289306
void RegBankLegalizeHelper::lower(MachineInstr &MI,
290307
const RegBankLLTMapping &Mapping,
291308
SmallSet<Register, 4> &WaterfallSgprs) {
@@ -372,6 +389,8 @@ void RegBankLegalizeHelper::lower(MachineInstr &MI,
372389
return lowerS_BFE(MI);
373390
case SplitTo32:
374391
return lowerSplitTo32(MI);
392+
case SplitTo32Sel:
393+
return lowerSplitTo32Sel(MI);
375394
case SplitLoad: {
376395
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
377396
unsigned Size = DstTy.getSizeInBits();
@@ -485,7 +504,8 @@ LLT RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
485504
case UniInVgprB64:
486505
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
487506
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(0, 64) ||
488-
Ty == LLT::pointer(1, 64) || Ty == LLT::pointer(4, 64))
507+
Ty == LLT::pointer(1, 64) || Ty == LLT::pointer(4, 64) ||
508+
(Ty.isPointer() && Ty.getAddressSpace() > AMDGPUAS::MAX_AMDGPU_ADDRESS))
489509
return Ty;
490510
return LLT();
491511
case SgprB96:

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,7 @@ class RegBankLegalizeHelper {
114114
void lowerV_BFE(MachineInstr &MI);
115115
void lowerS_BFE(MachineInstr &MI);
116116
void lowerSplitTo32(MachineInstr &MI);
117+
void lowerSplitTo32Sel(MachineInstr &MI);
117118
};
118119

119120
} // end namespace AMDGPU

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,8 @@ UniformityLLTOpPredicateID LLTToBId(LLT Ty) {
198198
return B32;
199199
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
200200
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(1, 64) ||
201-
Ty == LLT::pointer(4, 64))
201+
Ty == LLT::pointer(4, 64) ||
202+
(Ty.isPointer() && Ty.getAddressSpace() > AMDGPUAS::MAX_AMDGPU_ADDRESS))
202203
return B64;
203204
if (Ty == LLT::fixed_vector(3, 32))
204205
return B96;
@@ -485,8 +486,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
485486
addRulesForGOpcs({G_BR}).Any({{_}, {{}, {None}}});
486487

487488
addRulesForGOpcs({G_SELECT}, StandardB)
489+
.Any({{DivS16}, {{Vgpr16}, {Vcc, Vgpr16, Vgpr16}}})
490+
.Any({{UniS16}, {{Sgpr16}, {Sgpr32AExtBoolInReg, Sgpr16, Sgpr16}}})
488491
.Div(B32, {{VgprB32}, {Vcc, VgprB32, VgprB32}})
489-
.Uni(B32, {{SgprB32}, {Sgpr32AExtBoolInReg, SgprB32, SgprB32}});
492+
.Uni(B32, {{SgprB32}, {Sgpr32AExtBoolInReg, SgprB32, SgprB32}})
493+
.Div(B64, {{VgprB64}, {Vcc, VgprB64, VgprB64}, SplitTo32Sel})
494+
.Uni(B64, {{SgprB64}, {Sgpr32AExtBoolInReg, SgprB64, SgprB64}});
490495

491496
addRulesForGOpcs({G_ANYEXT})
492497
.Any({{UniS16, S1}, {{None}, {None}}}) // should be combined away

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,7 @@ enum LoweringMethodID {
177177
V_BFE,
178178
VgprToVccCopy,
179179
SplitTo32,
180+
SplitTo32Sel,
180181
Ext32To64,
181182
UniCstExt,
182183
SplitLoad,

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