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[RISCV] Relax RISCVInsertVSETVLI output VL peeking to cover registers (#96200)
If the AVL in a VSETVLIInfo is the output VL of a vsetvli with the same VLMAX, we treat it as the AVL of said vsetvli. This allows us to remove a true dependency as well as treating VSETVLIInfos as equal in more places and avoid toggles. We do this in two places, needVSETVLI and computeInfoForInstr. However we don't do this in computeInfoForInstr's vsetvli equivalent, getInfoForVSETVLI. We also have a restriction only in computeInfoForInstr that the AVL can't be a register as we want to avoid extending live ranges. This patch does two interlinked things: 1) It adds this AVL "peeking" to getInfoForVSETVLI 2) It relaxes the constraint that the AVL can't be a register in computeInfoForInstr, since it removes a use of the output VL which can actually reduce register pressure. E.g. see the diff in @vector_init_vsetvli_N and @test6 Now that getInfoForVSETVLI and computeInfoForInstr are consistent, we can remove the check in needVSETVLI. We also need to update how we update LiveIntervals in insertVSETVLI, as we can now end up needing to extend the LiveRange of the AVL across blocks.
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‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 20 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -962,6 +962,17 @@ RISCVInsertVSETVLI::getInfoForVSETVLI(const MachineInstr &MI) const {
962962
}
963963
NewInfo.setVTYPE(MI.getOperand(2).getImm());
964964

965+
// If AVL is defined by a vsetvli with the same VLMAX, we can replace the
966+
// AVL operand with the AVL of the defining vsetvli.
967+
if (NewInfo.hasAVLReg()) {
968+
if (const MachineInstr *DefMI = NewInfo.getAVLDefMI(LIS);
969+
DefMI && isVectorConfigInstr(*DefMI)) {
970+
VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI);
971+
if (DefInstrInfo.hasSameVLMAX(NewInfo))
972+
NewInfo.setAVL(DefInstrInfo);
973+
}
974+
}
975+
965976
return NewInfo;
966977
}
967978

@@ -1050,15 +1061,12 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const {
10501061
InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
10511062

10521063
// If AVL is defined by a vsetvli with the same VLMAX, we can replace the
1053-
// AVL operand with the AVL of the defining vsetvli. We avoid general
1054-
// register AVLs to avoid extending live ranges without being sure we can
1055-
// kill the original source reg entirely.
1064+
// AVL operand with the AVL of the defining vsetvli.
10561065
if (InstrInfo.hasAVLReg()) {
10571066
if (const MachineInstr *DefMI = InstrInfo.getAVLDefMI(LIS);
10581067
DefMI && isVectorConfigInstr(*DefMI)) {
10591068
VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI);
1060-
if (DefInstrInfo.hasSameVLMAX(InstrInfo) &&
1061-
(DefInstrInfo.hasAVLImm() || DefInstrInfo.hasAVLVLMAX()))
1069+
if (DefInstrInfo.hasSameVLMAX(InstrInfo))
10621070
InstrInfo.setAVL(DefInstrInfo);
10631071
}
10641072
}
@@ -1146,9 +1154,13 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
11461154
LIS->InsertMachineInstrInMaps(*MI);
11471155
// Normally the AVL's live range will already extend past the inserted
11481156
// vsetvli because the pseudos below will already use the AVL. But this
1149-
// isn't always the case, e.g. PseudoVMV_X_S doesn't have an AVL operand.
1150-
LIS->getInterval(AVLReg).extendInBlock(
1151-
LIS->getMBBStartIdx(&MBB), LIS->getInstructionIndex(*MI).getRegSlot());
1157+
// isn't always the case, e.g. PseudoVMV_X_S doesn't have an AVL operand or
1158+
// we've taken the AVL from the VL output of another vsetvli.
1159+
LiveInterval &LI = LIS->getInterval(AVLReg);
1160+
// Need to get non-const VNInfo
1161+
VNInfo *VNI = LI.getValNumInfo(Info.getAVLVNInfo()->id);
1162+
LI.addSegment(LiveInterval::Segment(
1163+
VNI->def, LIS->getInstructionIndex(*MI).getRegSlot(), VNI));
11521164
}
11531165
}
11541166

@@ -1163,19 +1175,6 @@ bool RISCVInsertVSETVLI::needVSETVLI(const DemandedFields &Used,
11631175
if (CurInfo.isCompatible(Used, Require, LIS))
11641176
return false;
11651177

1166-
// We didn't find a compatible value. If our AVL is a virtual register,
1167-
// it might be defined by a VSET(I)VLI. If it has the same VLMAX we need
1168-
// and the last VL/VTYPE we observed is the same, we don't need a
1169-
// VSETVLI here.
1170-
if (Require.hasAVLReg() && CurInfo.hasCompatibleVTYPE(Used, Require)) {
1171-
if (const MachineInstr *DefMI = Require.getAVLDefMI(LIS);
1172-
DefMI && isVectorConfigInstr(*DefMI)) {
1173-
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
1174-
if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
1175-
return false;
1176-
}
1177-
}
1178-
11791178
return true;
11801179
}
11811180

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

Lines changed: 25 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -234,41 +234,41 @@ if.end6: ; preds = %if.else5, %if.then4
234234
define <vscale x 1 x double> @test6(i64 %avl, i8 zeroext %cond, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
235235
; CHECK-LABEL: test6:
236236
; CHECK: # %bb.0: # %entry
237-
; CHECK-NEXT: andi a3, a1, 1
238-
; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, ma
239-
; CHECK-NEXT: bnez a3, .LBB5_3
237+
; CHECK-NEXT: andi a2, a1, 1
238+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
239+
; CHECK-NEXT: bnez a2, .LBB5_3
240240
; CHECK-NEXT: # %bb.1: # %if.else
241241
; CHECK-NEXT: vfsub.vv v8, v8, v9
242242
; CHECK-NEXT: andi a1, a1, 2
243243
; CHECK-NEXT: beqz a1, .LBB5_4
244244
; CHECK-NEXT: .LBB5_2: # %if.then4
245-
; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
246-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
247-
; CHECK-NEXT: vlse64.v v9, (a0), zero
248-
; CHECK-NEXT: lui a0, %hi(.LCPI5_1)
249-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_1)
250-
; CHECK-NEXT: vlse64.v v10, (a0), zero
245+
; CHECK-NEXT: lui a1, %hi(.LCPI5_0)
246+
; CHECK-NEXT: addi a1, a1, %lo(.LCPI5_0)
247+
; CHECK-NEXT: vlse64.v v9, (a1), zero
248+
; CHECK-NEXT: lui a1, %hi(.LCPI5_1)
249+
; CHECK-NEXT: addi a1, a1, %lo(.LCPI5_1)
250+
; CHECK-NEXT: vlse64.v v10, (a1), zero
251251
; CHECK-NEXT: vfadd.vv v9, v9, v10
252-
; CHECK-NEXT: lui a0, %hi(scratch)
253-
; CHECK-NEXT: addi a0, a0, %lo(scratch)
254-
; CHECK-NEXT: vse64.v v9, (a0)
252+
; CHECK-NEXT: lui a1, %hi(scratch)
253+
; CHECK-NEXT: addi a1, a1, %lo(scratch)
254+
; CHECK-NEXT: vse64.v v9, (a1)
255255
; CHECK-NEXT: j .LBB5_5
256256
; CHECK-NEXT: .LBB5_3: # %if.then
257257
; CHECK-NEXT: vfadd.vv v8, v8, v9
258258
; CHECK-NEXT: andi a1, a1, 2
259259
; CHECK-NEXT: bnez a1, .LBB5_2
260260
; CHECK-NEXT: .LBB5_4: # %if.else5
261261
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
262-
; CHECK-NEXT: lui a0, 260096
263-
; CHECK-NEXT: vmv.v.x v9, a0
264-
; CHECK-NEXT: lui a0, 262144
265-
; CHECK-NEXT: vmv.v.x v10, a0
262+
; CHECK-NEXT: lui a1, 260096
263+
; CHECK-NEXT: vmv.v.x v9, a1
264+
; CHECK-NEXT: lui a1, 262144
265+
; CHECK-NEXT: vmv.v.x v10, a1
266266
; CHECK-NEXT: vfadd.vv v9, v9, v10
267-
; CHECK-NEXT: lui a0, %hi(scratch)
268-
; CHECK-NEXT: addi a0, a0, %lo(scratch)
269-
; CHECK-NEXT: vse32.v v9, (a0)
267+
; CHECK-NEXT: lui a1, %hi(scratch)
268+
; CHECK-NEXT: addi a1, a1, %lo(scratch)
269+
; CHECK-NEXT: vse32.v v9, (a1)
270270
; CHECK-NEXT: .LBB5_5: # %if.end10
271-
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma
271+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
272272
; CHECK-NEXT: vfmul.vv v8, v8, v8
273273
; CHECK-NEXT: ret
274274
entry:
@@ -328,7 +328,8 @@ define <vscale x 1 x double> @test8(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
328328
; CHECK-NEXT: csrr a2, vlenb
329329
; CHECK-NEXT: slli a2, a2, 1
330330
; CHECK-NEXT: sub sp, sp, a2
331-
; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, ma
331+
; CHECK-NEXT: mv s0, a0
332+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
332333
; CHECK-NEXT: beqz a1, .LBB6_2
333334
; CHECK-NEXT: # %bb.1: # %if.then
334335
; CHECK-NEXT: vfadd.vv v8, v8, v9
@@ -387,7 +388,8 @@ define <vscale x 1 x double> @test9(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
387388
; CHECK-NEXT: csrr a2, vlenb
388389
; CHECK-NEXT: slli a2, a2, 1
389390
; CHECK-NEXT: sub sp, sp, a2
390-
; CHECK-NEXT: vsetvli s0, a0, e64, m1, ta, ma
391+
; CHECK-NEXT: mv s0, a0
392+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
391393
; CHECK-NEXT: beqz a1, .LBB7_2
392394
; CHECK-NEXT: # %bb.1: # %if.then
393395
; CHECK-NEXT: vfadd.vv v9, v8, v9
@@ -722,7 +724,7 @@ define void @vector_init_vsetvli_N(i64 %N, ptr %c) {
722724
; CHECK-NEXT: vmv.v.i v8, 0
723725
; CHECK-NEXT: .LBB14_2: # %for.body
724726
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
725-
; CHECK-NEXT: vsetvli zero, a3, e64, m1, ta, ma
727+
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
726728
; CHECK-NEXT: vse64.v v8, (a1)
727729
; CHECK-NEXT: add a2, a2, a3
728730
; CHECK-NEXT: add a1, a1, a4

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -258,7 +258,6 @@ entry:
258258
define <vscale x 1 x double> @test14(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
259259
; CHECK-LABEL: test14:
260260
; CHECK: # %bb.0: # %entry
261-
; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma
262261
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
263262
; CHECK-NEXT: vfadd.vv v8, v8, v9
264263
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma

‎llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@ define ptr @foo(ptr %a0, ptr %a1, i64 %a2) {
2020
; CHECK-NEXT: mv a3, a0
2121
; CHECK-NEXT: .LBB0_3: # %do.body
2222
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
23-
; CHECK-NEXT: vsetvli zero, a4, e8, m8, ta, ma
2423
; CHECK-NEXT: vle8.v v8, (a1)
2524
; CHECK-NEXT: vse8.v v8, (a3)
2625
; CHECK-NEXT: add a3, a3, a4

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