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[M68k] Correctly emit non-pic relocations (#89863)
The m68k backend will always emit external calls (including libcalls) with PC-relative PLT relocations, even when in non-pic mode or -fno-plt is used. This is unexpected, as other function calls are emitted with absolute addressing, and a static code modes suggests that there is no PLT. It also leads to a miscompilation where the call instruction emitted expects an immediate address, while the relocation emitted for that instruction is PC-relative. This miscompilation can even be seen in the default C function in godbolt: https://godbolt.org/z/zEoazovzo Fix the issue by classifying external function references based upon the pic mode. This triggers a change in the static code model, making it more in line with the expected behaviour and allowing use of this backend in more bare-metal situations where a PLT does not exist. The change avoids the issue where we emit a PLT32 relocation for an absolute call, and makes libcalls and other external calls use absolute addressing modes when a static code model is desired. Further work should be done in instruction lowering and validation to ensure that miscompilations of the same type don't occur.
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lines changed

15 files changed

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lines changed

‎llvm/lib/Target/M68k/M68kSubtarget.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -251,6 +251,6 @@ M68kSubtarget::classifyGlobalFunctionReference(const GlobalValue *GV,
251251
return M68kII::MO_GOTPCREL;
252252
}
253253

254-
// otherwise linker will figure this out
255-
return M68kII::MO_PLT;
254+
// Ensure that we don't emit PLT relocations when in non-pic modes.
255+
return isPositionIndependent() ? M68kII::MO_PLT : M68kII::MO_ABSOLUTE_ADDRESS;
256256
}

‎llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ define i32 @test5(i32 %A) nounwind {
7777
; CHECK-NEXT: suba.l #12, %sp
7878
; CHECK-NEXT: move.l #1577682821, (4,%sp)
7979
; CHECK-NEXT: move.l (16,%sp), (%sp)
80-
; CHECK-NEXT: jsr __udivsi3@PLT
80+
; CHECK-NEXT: jsr __udivsi3
8181
; CHECK-NEXT: adda.l #12, %sp
8282
; CHECK-NEXT: rts
8383
%tmp1 = udiv i32 %A, 1577682821 ; <i32> [#uses=1]
@@ -114,7 +114,7 @@ define i32 @test7(i32 %x) nounwind {
114114
; CHECK-NEXT: suba.l #12, %sp
115115
; CHECK-NEXT: move.l #28, (4,%sp)
116116
; CHECK-NEXT: move.l (16,%sp), (%sp)
117-
; CHECK-NEXT: jsr __udivsi3@PLT
117+
; CHECK-NEXT: jsr __udivsi3
118118
; CHECK-NEXT: adda.l #12, %sp
119119
; CHECK-NEXT: rts
120120
%div = udiv i32 %x, 28
@@ -178,7 +178,7 @@ define i32 @testsize2(i32 %x) minsize nounwind {
178178
; CHECK-NEXT: suba.l #12, %sp
179179
; CHECK-NEXT: move.l #33, (4,%sp)
180180
; CHECK-NEXT: move.l (16,%sp), (%sp)
181-
; CHECK-NEXT: jsr __divsi3@PLT
181+
; CHECK-NEXT: jsr __divsi3
182182
; CHECK-NEXT: adda.l #12, %sp
183183
; CHECK-NEXT: rts
184184
entry:
@@ -203,7 +203,7 @@ define i32 @testsize4(i32 %x) minsize nounwind {
203203
; CHECK-NEXT: suba.l #12, %sp
204204
; CHECK-NEXT: move.l #33, (4,%sp)
205205
; CHECK-NEXT: move.l (16,%sp), (%sp)
206-
; CHECK-NEXT: jsr __udivsi3@PLT
206+
; CHECK-NEXT: jsr __udivsi3
207207
; CHECK-NEXT: adda.l #12, %sp
208208
; CHECK-NEXT: rts
209209
entry:

‎llvm/test/CodeGen/M68k/Arith/imul.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ define i32 @mul_32(i32 %a, i32 %b) {
116116
; CHECK-NEXT: .cfi_def_cfa_offset -16
117117
; CHECK-NEXT: move.l (20,%sp), (4,%sp)
118118
; CHECK-NEXT: move.l (16,%sp), (%sp)
119-
; CHECK-NEXT: jsr __mulsi3@PLT
119+
; CHECK-NEXT: jsr __mulsi3
120120
; CHECK-NEXT: adda.l #12, %sp
121121
; CHECK-NEXT: rts
122122
%mul = mul i32 %a, %b
@@ -162,7 +162,7 @@ define i64 @mul_64(i64 %a, i64 %b) {
162162
; CHECK-NEXT: move.l (32,%sp), (8,%sp)
163163
; CHECK-NEXT: move.l (28,%sp), (4,%sp)
164164
; CHECK-NEXT: move.l (24,%sp), (%sp)
165-
; CHECK-NEXT: jsr __muldi3@PLT
165+
; CHECK-NEXT: jsr __muldi3
166166
; CHECK-NEXT: adda.l #20, %sp
167167
; CHECK-NEXT: rts
168168
%mul = mul i64 %a, %b
@@ -179,7 +179,7 @@ define i64 @mul3_64(i64 %A) {
179179
; CHECK-NEXT: move.l #0, (8,%sp)
180180
; CHECK-NEXT: move.l (28,%sp), (4,%sp)
181181
; CHECK-NEXT: move.l (24,%sp), (%sp)
182-
; CHECK-NEXT: jsr __muldi3@PLT
182+
; CHECK-NEXT: jsr __muldi3
183183
; CHECK-NEXT: adda.l #20, %sp
184184
; CHECK-NEXT: rts
185185
%mul = mul i64 %A, 3
@@ -196,7 +196,7 @@ define i64 @mul40_64(i64 %A) {
196196
; CHECK-NEXT: move.l #0, (8,%sp)
197197
; CHECK-NEXT: move.l (28,%sp), (4,%sp)
198198
; CHECK-NEXT: move.l (24,%sp), (%sp)
199-
; CHECK-NEXT: jsr __muldi3@PLT
199+
; CHECK-NEXT: jsr __muldi3
200200
; CHECK-NEXT: adda.l #20, %sp
201201
; CHECK-NEXT: rts
202202
%mul = mul i64 %A, 40

‎llvm/test/CodeGen/M68k/Arith/mul64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ define i64 @foo(i64 %t, i64 %u) nounwind {
1111
; CHECK-NEXT: move.l (32,%sp), (8,%sp)
1212
; CHECK-NEXT: move.l (28,%sp), (4,%sp)
1313
; CHECK-NEXT: move.l (24,%sp), (%sp)
14-
; CHECK-NEXT: jsr __muldi3@PLT
14+
; CHECK-NEXT: jsr __muldi3
1515
; CHECK-NEXT: adda.l #20, %sp
1616
; CHECK-NEXT: rts
1717
%k = mul i64 %t, %u

‎llvm/test/CodeGen/M68k/Arith/sdiv-exact.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ define i32 @test1(i32 %x) {
99
; CHECK-NEXT: .cfi_def_cfa_offset -16
1010
; CHECK-NEXT: move.l #-1030792151, (4,%sp)
1111
; CHECK-NEXT: move.l (16,%sp), (%sp)
12-
; CHECK-NEXT: jsr __mulsi3@PLT
12+
; CHECK-NEXT: jsr __mulsi3
1313
; CHECK-NEXT: adda.l #12, %sp
1414
; CHECK-NEXT: rts
1515
%div = sdiv exact i32 %x, 25
@@ -26,7 +26,7 @@ define i32 @test2(i32 %x) {
2626
; CHECK-NEXT: asr.l #3, %d0
2727
; CHECK-NEXT: move.l %d0, (%sp)
2828
; CHECK-NEXT: move.l #-1431655765, (4,%sp)
29-
; CHECK-NEXT: jsr __mulsi3@PLT
29+
; CHECK-NEXT: jsr __mulsi3
3030
; CHECK-NEXT: adda.l #12, %sp
3131
; CHECK-NEXT: rts
3232
%div = sdiv exact i32 %x, 24

‎llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -69,15 +69,15 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind {
6969
; CHECK-NEXT: ; %bb.2: ; %overflow
7070
; CHECK-NEXT: lea (no,%pc), %a0
7171
; CHECK-NEXT: move.l %a0, (%sp)
72-
; CHECK-NEXT: jsr printf@PLT
72+
; CHECK-NEXT: jsr printf
7373
; CHECK-NEXT: moveq #0, %d0
7474
; CHECK-NEXT: adda.l #12, %sp
7575
; CHECK-NEXT: rts
7676
; CHECK-NEXT: .LBB3_1: ; %normal
7777
; CHECK-NEXT: move.l %d0, (4,%sp)
7878
; CHECK-NEXT: lea (ok,%pc), %a0
7979
; CHECK-NEXT: move.l %a0, (%sp)
80-
; CHECK-NEXT: jsr printf@PLT
80+
; CHECK-NEXT: jsr printf
8181
; CHECK-NEXT: moveq #1, %d0
8282
; CHECK-NEXT: adda.l #12, %sp
8383
; CHECK-NEXT: rts
@@ -107,15 +107,15 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
107107
; CHECK-NEXT: ; %bb.1: ; %overflow
108108
; CHECK-NEXT: lea (no,%pc), %a0
109109
; CHECK-NEXT: move.l %a0, (%sp)
110-
; CHECK-NEXT: jsr printf@PLT
110+
; CHECK-NEXT: jsr printf
111111
; CHECK-NEXT: moveq #0, %d0
112112
; CHECK-NEXT: adda.l #12, %sp
113113
; CHECK-NEXT: rts
114114
; CHECK-NEXT: .LBB4_2: ; %normal
115115
; CHECK-NEXT: move.l %d0, (4,%sp)
116116
; CHECK-NEXT: lea (ok,%pc), %a0
117117
; CHECK-NEXT: move.l %a0, (%sp)
118-
; CHECK-NEXT: jsr printf@PLT
118+
; CHECK-NEXT: jsr printf
119119
; CHECK-NEXT: moveq #1, %d0
120120
; CHECK-NEXT: adda.l #12, %sp
121121
; CHECK-NEXT: rts

‎llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,15 +18,15 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind {
1818
; CHECK-NEXT: ; %bb.2: ; %overflow
1919
; CHECK-NEXT: lea (no,%pc), %a0
2020
; CHECK-NEXT: move.l %a0, (%sp)
21-
; CHECK-NEXT: jsr printf@PLT
21+
; CHECK-NEXT: jsr printf
2222
; CHECK-NEXT: moveq #0, %d0
2323
; CHECK-NEXT: adda.l #12, %sp
2424
; CHECK-NEXT: rts
2525
; CHECK-NEXT: .LBB0_1: ; %normal
2626
; CHECK-NEXT: move.l %d0, (4,%sp)
2727
; CHECK-NEXT: lea (ok,%pc), %a0
2828
; CHECK-NEXT: move.l %a0, (%sp)
29-
; CHECK-NEXT: jsr printf@PLT
29+
; CHECK-NEXT: jsr printf
3030
; CHECK-NEXT: moveq #1, %d0
3131
; CHECK-NEXT: adda.l #12, %sp
3232
; CHECK-NEXT: rts
@@ -55,15 +55,15 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind {
5555
; CHECK-NEXT: ; %bb.2: ; %carry
5656
; CHECK-NEXT: lea (no,%pc), %a0
5757
; CHECK-NEXT: move.l %a0, (%sp)
58-
; CHECK-NEXT: jsr printf@PLT
58+
; CHECK-NEXT: jsr printf
5959
; CHECK-NEXT: moveq #0, %d0
6060
; CHECK-NEXT: adda.l #12, %sp
6161
; CHECK-NEXT: rts
6262
; CHECK-NEXT: .LBB1_1: ; %normal
6363
; CHECK-NEXT: move.l %d0, (4,%sp)
6464
; CHECK-NEXT: lea (ok,%pc), %a0
6565
; CHECK-NEXT: move.l %a0, (%sp)
66-
; CHECK-NEXT: jsr printf@PLT
66+
; CHECK-NEXT: jsr printf
6767
; CHECK-NEXT: moveq #1, %d0
6868
; CHECK-NEXT: adda.l #12, %sp
6969
; CHECK-NEXT: rts

‎llvm/test/CodeGen/M68k/Atomics/cmpxchg.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define i1 @cmpxchg_i8_monotonic_monotonic(i8 %cmp, i8 %new, ptr %mem) nounwind {
1818
; NO-ATOMIC-NEXT: and.l #255, %d0
1919
; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
2020
; NO-ATOMIC-NEXT: move.l (32,%sp), (%sp)
21-
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_1@PLT
21+
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_1
2222
; NO-ATOMIC-NEXT: sub.b %d2, %d0
2323
; NO-ATOMIC-NEXT: seq %d0
2424
; NO-ATOMIC-NEXT: movem.l (16,%sp), %d2 ; 8-byte Folded Reload
@@ -55,7 +55,7 @@ define i16 @cmpxchg_i16_release_monotonic(i16 %cmp, i16 %new, ptr %mem) nounwind
5555
; NO-ATOMIC-NEXT: and.l #65535, %d0
5656
; NO-ATOMIC-NEXT: move.l %d0, (4,%sp)
5757
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
58-
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_2@PLT
58+
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_2
5959
; NO-ATOMIC-NEXT: adda.l #12, %sp
6060
; NO-ATOMIC-NEXT: rts
6161
;
@@ -78,7 +78,7 @@ define i32 @cmpxchg_i32_release_acquire(i32 %cmp, i32 %new, ptr %mem) nounwind {
7878
; NO-ATOMIC-NEXT: move.l (20,%sp), (8,%sp)
7979
; NO-ATOMIC-NEXT: move.l (16,%sp), (4,%sp)
8080
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
81-
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_4@PLT
81+
; NO-ATOMIC-NEXT: jsr __sync_val_compare_and_swap_4
8282
; NO-ATOMIC-NEXT: adda.l #12, %sp
8383
; NO-ATOMIC-NEXT: rts
8484
;
@@ -107,7 +107,7 @@ define i64 @cmpxchg_i64_seqcst_seqcst(i64 %cmp, i64 %new, ptr %mem) nounwind {
107107
; NO-ATOMIC-NEXT: move.l (52,%sp), (12,%sp)
108108
; NO-ATOMIC-NEXT: move.l (48,%sp), (8,%sp)
109109
; NO-ATOMIC-NEXT: move.l (56,%sp), (%sp)
110-
; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_8@PLT
110+
; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_8
111111
; NO-ATOMIC-NEXT: move.l (28,%sp), %d1
112112
; NO-ATOMIC-NEXT: move.l (24,%sp), %d0
113113
; NO-ATOMIC-NEXT: adda.l #36, %sp
@@ -125,7 +125,7 @@ define i64 @cmpxchg_i64_seqcst_seqcst(i64 %cmp, i64 %new, ptr %mem) nounwind {
125125
; ATOMIC-NEXT: move.l (52,%sp), (12,%sp)
126126
; ATOMIC-NEXT: move.l (48,%sp), (8,%sp)
127127
; ATOMIC-NEXT: move.l (56,%sp), (%sp)
128-
; ATOMIC-NEXT: jsr __atomic_compare_exchange_8@PLT
128+
; ATOMIC-NEXT: jsr __atomic_compare_exchange_8
129129
; ATOMIC-NEXT: move.l (28,%sp), %d1
130130
; ATOMIC-NEXT: move.l (24,%sp), %d0
131131
; ATOMIC-NEXT: adda.l #36, %sp

‎llvm/test/CodeGen/M68k/Atomics/load-store.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,7 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind {
203203
; NO-ATOMIC-NEXT: suba.l #12, %sp
204204
; NO-ATOMIC-NEXT: move.l #0, (4,%sp)
205205
; NO-ATOMIC-NEXT: move.l (16,%sp), (%sp)
206-
; NO-ATOMIC-NEXT: jsr __atomic_load_8@PLT
206+
; NO-ATOMIC-NEXT: jsr __atomic_load_8
207207
; NO-ATOMIC-NEXT: adda.l #12, %sp
208208
; NO-ATOMIC-NEXT: rts
209209
;
@@ -212,7 +212,7 @@ define i64 @atomic_load_i64_unordered(ptr %a) nounwind {
212212
; ATOMIC-NEXT: suba.l #12, %sp
213213
; ATOMIC-NEXT: move.l #0, (4,%sp)
214214
; ATOMIC-NEXT: move.l (16,%sp), (%sp)
215-
; ATOMIC-NEXT: jsr __atomic_load_8@PLT
215+
; ATOMIC-NEXT: jsr __atomic_load_8
216216
; ATOMIC-NEXT: adda.l #12, %sp
217217
; ATOMIC-NEXT: rts
218218
%1 = load atomic i64, ptr %a unordered, align 8
@@ -225,7 +225,7 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind {
225225
; NO-ATOMIC-NEXT: suba.l #12, %sp
226226
; NO-ATOMIC-NEXT: move.l #0, (4,%sp)
227227
; NO-ATOMIC-NEXT: move.l (16,%sp), (%sp)
228-
; NO-ATOMIC-NEXT: jsr __atomic_load_8@PLT
228+
; NO-ATOMIC-NEXT: jsr __atomic_load_8
229229
; NO-ATOMIC-NEXT: adda.l #12, %sp
230230
; NO-ATOMIC-NEXT: rts
231231
;
@@ -234,7 +234,7 @@ define i64 @atomic_load_i64_monotonic(ptr %a) nounwind {
234234
; ATOMIC-NEXT: suba.l #12, %sp
235235
; ATOMIC-NEXT: move.l #0, (4,%sp)
236236
; ATOMIC-NEXT: move.l (16,%sp), (%sp)
237-
; ATOMIC-NEXT: jsr __atomic_load_8@PLT
237+
; ATOMIC-NEXT: jsr __atomic_load_8
238238
; ATOMIC-NEXT: adda.l #12, %sp
239239
; ATOMIC-NEXT: rts
240240
%1 = load atomic i64, ptr %a monotonic, align 8
@@ -247,7 +247,7 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
247247
; NO-ATOMIC-NEXT: suba.l #12, %sp
248248
; NO-ATOMIC-NEXT: move.l #2, (4,%sp)
249249
; NO-ATOMIC-NEXT: move.l (16,%sp), (%sp)
250-
; NO-ATOMIC-NEXT: jsr __atomic_load_8@PLT
250+
; NO-ATOMIC-NEXT: jsr __atomic_load_8
251251
; NO-ATOMIC-NEXT: adda.l #12, %sp
252252
; NO-ATOMIC-NEXT: rts
253253
;
@@ -256,7 +256,7 @@ define i64 @atomic_load_i64_acquire(ptr %a) nounwind {
256256
; ATOMIC-NEXT: suba.l #12, %sp
257257
; ATOMIC-NEXT: move.l #2, (4,%sp)
258258
; ATOMIC-NEXT: move.l (16,%sp), (%sp)
259-
; ATOMIC-NEXT: jsr __atomic_load_8@PLT
259+
; ATOMIC-NEXT: jsr __atomic_load_8
260260
; ATOMIC-NEXT: adda.l #12, %sp
261261
; ATOMIC-NEXT: rts
262262
%1 = load atomic i64, ptr %a acquire, align 8
@@ -269,7 +269,7 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
269269
; NO-ATOMIC-NEXT: suba.l #12, %sp
270270
; NO-ATOMIC-NEXT: move.l #5, (4,%sp)
271271
; NO-ATOMIC-NEXT: move.l (16,%sp), (%sp)
272-
; NO-ATOMIC-NEXT: jsr __atomic_load_8@PLT
272+
; NO-ATOMIC-NEXT: jsr __atomic_load_8
273273
; NO-ATOMIC-NEXT: adda.l #12, %sp
274274
; NO-ATOMIC-NEXT: rts
275275
;
@@ -278,7 +278,7 @@ define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind {
278278
; ATOMIC-NEXT: suba.l #12, %sp
279279
; ATOMIC-NEXT: move.l #5, (4,%sp)
280280
; ATOMIC-NEXT: move.l (16,%sp), (%sp)
281-
; ATOMIC-NEXT: jsr __atomic_load_8@PLT
281+
; ATOMIC-NEXT: jsr __atomic_load_8
282282
; ATOMIC-NEXT: adda.l #12, %sp
283283
; ATOMIC-NEXT: rts
284284
%1 = load atomic i64, ptr %a seq_cst, align 8
@@ -509,7 +509,7 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %val) nounwind {
509509
; NO-ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
510510
; NO-ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
511511
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
512-
; NO-ATOMIC-NEXT: jsr __atomic_store_8@PLT
512+
; NO-ATOMIC-NEXT: jsr __atomic_store_8
513513
; NO-ATOMIC-NEXT: adda.l #20, %sp
514514
; NO-ATOMIC-NEXT: rts
515515
;
@@ -520,7 +520,7 @@ define void @atomic_store_i64_unordered(ptr %a, i64 %val) nounwind {
520520
; ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
521521
; ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
522522
; ATOMIC-NEXT: move.l (24,%sp), (%sp)
523-
; ATOMIC-NEXT: jsr __atomic_store_8@PLT
523+
; ATOMIC-NEXT: jsr __atomic_store_8
524524
; ATOMIC-NEXT: adda.l #20, %sp
525525
; ATOMIC-NEXT: rts
526526
store atomic i64 %val, ptr %a unordered, align 8
@@ -535,7 +535,7 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %val) nounwind {
535535
; NO-ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
536536
; NO-ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
537537
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
538-
; NO-ATOMIC-NEXT: jsr __atomic_store_8@PLT
538+
; NO-ATOMIC-NEXT: jsr __atomic_store_8
539539
; NO-ATOMIC-NEXT: adda.l #20, %sp
540540
; NO-ATOMIC-NEXT: rts
541541
;
@@ -546,7 +546,7 @@ define void @atomic_store_i64_monotonic(ptr %a, i64 %val) nounwind {
546546
; ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
547547
; ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
548548
; ATOMIC-NEXT: move.l (24,%sp), (%sp)
549-
; ATOMIC-NEXT: jsr __atomic_store_8@PLT
549+
; ATOMIC-NEXT: jsr __atomic_store_8
550550
; ATOMIC-NEXT: adda.l #20, %sp
551551
; ATOMIC-NEXT: rts
552552
store atomic i64 %val, ptr %a monotonic, align 8
@@ -561,7 +561,7 @@ define void @atomic_store_i64_release(ptr %a, i64 %val) nounwind {
561561
; NO-ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
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; NO-ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
563563
; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
564-
; NO-ATOMIC-NEXT: jsr __atomic_store_8@PLT
564+
; NO-ATOMIC-NEXT: jsr __atomic_store_8
565565
; NO-ATOMIC-NEXT: adda.l #20, %sp
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; NO-ATOMIC-NEXT: rts
567567
;
@@ -572,7 +572,7 @@ define void @atomic_store_i64_release(ptr %a, i64 %val) nounwind {
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; ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
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; ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
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; ATOMIC-NEXT: move.l (24,%sp), (%sp)
575-
; ATOMIC-NEXT: jsr __atomic_store_8@PLT
575+
; ATOMIC-NEXT: jsr __atomic_store_8
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; ATOMIC-NEXT: adda.l #20, %sp
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; ATOMIC-NEXT: rts
578578
store atomic i64 %val, ptr %a release, align 8
@@ -587,7 +587,7 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %val) nounwind {
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; NO-ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
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; NO-ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
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; NO-ATOMIC-NEXT: move.l (24,%sp), (%sp)
590-
; NO-ATOMIC-NEXT: jsr __atomic_store_8@PLT
590+
; NO-ATOMIC-NEXT: jsr __atomic_store_8
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; NO-ATOMIC-NEXT: adda.l #20, %sp
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; NO-ATOMIC-NEXT: rts
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;
@@ -598,7 +598,7 @@ define void @atomic_store_i64_seq_cst(ptr %a, i64 %val) nounwind {
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; ATOMIC-NEXT: move.l (32,%sp), (8,%sp)
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; ATOMIC-NEXT: move.l (28,%sp), (4,%sp)
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; ATOMIC-NEXT: move.l (24,%sp), (%sp)
601-
; ATOMIC-NEXT: jsr __atomic_store_8@PLT
601+
; ATOMIC-NEXT: jsr __atomic_store_8
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; ATOMIC-NEXT: adda.l #20, %sp
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; ATOMIC-NEXT: rts
604604
store atomic i64 %val, ptr %a seq_cst, align 8

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