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michalpaszkowskimichalpaszkowski
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[SPIR-V] Remove -opaque-pointers=0 from LITs, fixes for opaque pointers support
Differential Revision: https://reviews.llvm.org/D156049
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55 files changed

+596
-655
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‎llvm/include/llvm/IR/IntrinsicsSPIRV.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212

1313
let TargetPrefix = "spv" in {
1414
def int_spv_assign_type : Intrinsic<[], [llvm_any_ty, llvm_metadata_ty]>;
15+
def int_spv_assign_ptr_type : Intrinsic<[], [llvm_any_ty, llvm_metadata_ty]>;
1516
def int_spv_assign_name : Intrinsic<[], [llvm_any_ty, llvm_vararg_ty]>;
1617

1718
def int_spv_track_constant : Intrinsic<[llvm_any_ty], [llvm_any_ty, llvm_metadata_ty]>;

‎llvm/lib/Target/SPIRV/SPIRVDuplicatesTracker.h

Lines changed: 34 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ struct SpecialTypeDescriptor {
5959
STK_Sampler,
6060
STK_Pipe,
6161
STK_DeviceEvent,
62+
STK_Pointer,
6263
STK_Last = -1
6364
};
6465
SpecialTypeKind Kind;
@@ -160,6 +161,23 @@ struct DeviceEventTypeDescriptor : public SpecialTypeDescriptor {
160161
return TD->Kind == SpecialTypeKind::STK_DeviceEvent;
161162
}
162163
};
164+
165+
struct PointerTypeDescriptor : public SpecialTypeDescriptor {
166+
const Type *ElementType;
167+
unsigned AddressSpace;
168+
169+
PointerTypeDescriptor() = delete;
170+
PointerTypeDescriptor(const Type *ElementType, unsigned AddressSpace)
171+
: SpecialTypeDescriptor(SpecialTypeKind::STK_Pointer),
172+
ElementType(ElementType), AddressSpace(AddressSpace) {
173+
Hash = (DenseMapInfo<Type *>().getHashValue(ElementType) & 0xffff) ^
174+
((AddressSpace << 8) | Kind);
175+
}
176+
177+
static bool classof(const SpecialTypeDescriptor *TD) {
178+
return TD->Kind == SpecialTypeKind::STK_Pointer;
179+
}
180+
};
163181
} // namespace SPIRV
164182

165183
template <> struct DenseMapInfo<SPIRV::SpecialTypeDescriptor> {
@@ -262,8 +280,14 @@ class SPIRVGeneralDuplicatesTracker {
262280
void buildDepsGraph(std::vector<SPIRV::DTSortableEntry *> &Graph,
263281
MachineModuleInfo *MMI);
264282

265-
void add(const Type *T, const MachineFunction *MF, Register R) {
266-
TT.add(T, MF, R);
283+
void add(const Type *Ty, const MachineFunction *MF, Register R) {
284+
TT.add(Ty, MF, R);
285+
}
286+
287+
void add(const Type *PointerElementType, unsigned AddressSpace,
288+
const MachineFunction *MF, Register R) {
289+
ST.add(SPIRV::PointerTypeDescriptor(PointerElementType, AddressSpace), MF,
290+
R);
267291
}
268292

269293
void add(const Constant *C, const MachineFunction *MF, Register R) {
@@ -287,8 +311,14 @@ class SPIRVGeneralDuplicatesTracker {
287311
ST.add(TD, MF, R);
288312
}
289313

290-
Register find(const Type *T, const MachineFunction *MF) {
291-
return TT.find(const_cast<Type *>(T), MF);
314+
Register find(const Type *Ty, const MachineFunction *MF) {
315+
return TT.find(const_cast<Type *>(Ty), MF);
316+
}
317+
318+
Register find(const Type *PointerElementType, unsigned AddressSpace,
319+
const MachineFunction *MF) {
320+
return ST.find(
321+
SPIRV::PointerTypeDescriptor(PointerElementType, AddressSpace), MF);
292322
}
293323

294324
Register find(const Constant *C, const MachineFunction *MF) {

‎llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ class SPIRVEmitIntrinsics
6666
}
6767
void replaceMemInstrUses(Instruction *Old, Instruction *New);
6868
void processInstrAfterVisit(Instruction *I);
69+
void insertAssignPtrTypeIntrs(Instruction *I);
6970
void insertAssignTypeIntrs(Instruction *I);
7071
void processGlobalValue(GlobalVariable &GV);
7172

@@ -387,9 +388,21 @@ void SPIRVEmitIntrinsics::processGlobalValue(GlobalVariable &GV) {
387388
IRB->CreateIntrinsic(Intrinsic::spv_unref_global, GV.getType(), &GV);
388389
}
389390

391+
void SPIRVEmitIntrinsics::insertAssignPtrTypeIntrs(Instruction *I) {
392+
if (I->getType()->isVoidTy() || !requireAssignType(I))
393+
return;
394+
395+
setInsertPointSkippingPhis(*IRB, I->getNextNode());
396+
if (auto *AI = dyn_cast<AllocaInst>(I)) {
397+
Constant *Const = Constant::getNullValue(AI->getAllocatedType());
398+
buildIntrWithMD(Intrinsic::spv_assign_ptr_type, {I->getType()}, Const, I);
399+
}
400+
}
401+
390402
void SPIRVEmitIntrinsics::insertAssignTypeIntrs(Instruction *I) {
391403
Type *Ty = I->getType();
392-
if (!Ty->isVoidTy() && requireAssignType(I)) {
404+
if (!Ty->isVoidTy() && requireAssignType(I) &&
405+
I->getOpcode() != Instruction::Alloca) {
393406
setInsertPointSkippingPhis(*IRB, I->getNextNode());
394407
Type *TypeToAssign = Ty;
395408
if (auto *II = dyn_cast<IntrinsicInst>(I)) {
@@ -484,8 +497,10 @@ bool SPIRVEmitIntrinsics::runOnFunction(Function &Func) {
484497
for (auto &I : instructions(Func))
485498
Worklist.push_back(&I);
486499

487-
for (auto &I : Worklist)
500+
for (auto &I : Worklist) {
501+
insertAssignPtrTypeIntrs(I);
488502
insertAssignTypeIntrs(I);
503+
}
489504

490505
for (auto *I : Worklist) {
491506
TrackConstants = true;

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

Lines changed: 47 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -638,6 +638,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeFunctionWithArgs(
638638
if (Reg.isValid())
639639
return getSPIRVTypeForVReg(Reg);
640640
SPIRVType *SpirvType = getOpTypeFunction(RetType, ArgTypes, MIRBuilder);
641+
DT.add(Ty, CurMF, getSPIRVTypeID(SpirvType));
641642
return finishCreatingSPIRVType(Ty, SpirvType);
642643
}
643644

@@ -748,8 +749,17 @@ SPIRVType *SPIRVGlobalRegistry::restOfCreateSPIRVType(
748749
// Do not add OpTypeForwardPointer to DT, a corresponding normal pointer type
749750
// will be added later. For special types it is already added to DT.
750751
if (SpirvType->getOpcode() != SPIRV::OpTypeForwardPointer && !Reg.isValid() &&
751-
!isSpecialOpaqueType(Ty))
752-
DT.add(Ty, &MIRBuilder.getMF(), getSPIRVTypeID(SpirvType));
752+
!isSpecialOpaqueType(Ty)) {
753+
if (!Ty->isPointerTy())
754+
DT.add(Ty, &MIRBuilder.getMF(), getSPIRVTypeID(SpirvType));
755+
else if (Ty->isOpaquePointerTy())
756+
DT.add(Type::getInt8Ty(MIRBuilder.getMF().getFunction().getContext()),
757+
Ty->getPointerAddressSpace(), &MIRBuilder.getMF(),
758+
getSPIRVTypeID(SpirvType));
759+
else
760+
DT.add(Ty->getNonOpaquePointerElementType(), Ty->getPointerAddressSpace(),
761+
&MIRBuilder.getMF(), getSPIRVTypeID(SpirvType));
762+
}
753763

754764
return SpirvType;
755765
}
@@ -767,7 +777,14 @@ SPIRVType *SPIRVGlobalRegistry::getSPIRVTypeForVReg(Register VReg) const {
767777
SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVType(
768778
const Type *Ty, MachineIRBuilder &MIRBuilder,
769779
SPIRV::AccessQualifier::AccessQualifier AccessQual, bool EmitIR) {
770-
Register Reg = DT.find(Ty, &MIRBuilder.getMF());
780+
Register Reg;
781+
if (!Ty->isPointerTy())
782+
Reg = DT.find(Ty, &MIRBuilder.getMF());
783+
else
784+
Reg =
785+
DT.find(Type::getInt8Ty(MIRBuilder.getMF().getFunction().getContext()),
786+
Ty->getPointerAddressSpace(), &MIRBuilder.getMF());
787+
771788
if (Reg.isValid() && !isSpecialOpaqueType(Ty))
772789
return getSPIRVTypeForVReg(Reg);
773790
TypesInProcessing.clear();
@@ -921,8 +938,9 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateOpTypeByOpcode(
921938
if (ResVReg.isValid())
922939
return MIRBuilder.getMF().getRegInfo().getUniqueVRegDef(ResVReg);
923940
ResVReg = createTypeVReg(MIRBuilder);
941+
SPIRVType *SpirvTy = MIRBuilder.buildInstr(Opcode).addDef(ResVReg);
924942
DT.add(Ty, &MIRBuilder.getMF(), ResVReg);
925-
return MIRBuilder.buildInstr(Opcode).addDef(ResVReg);
943+
return SpirvTy;
926944
}
927945

928946
const MachineInstr *
@@ -985,7 +1003,6 @@ SPIRVType *SPIRVGlobalRegistry::finishCreatingSPIRVType(const Type *LLVMTy,
9851003
assert(CurMF == SpirvType->getMF());
9861004
VRegToTypeMap[CurMF][getSPIRVTypeID(SpirvType)] = SpirvType;
9871005
SPIRVToLLVMType[SpirvType] = LLVMTy;
988-
DT.add(LLVMTy, CurMF, getSPIRVTypeID(SpirvType));
9891006
return SpirvType;
9901007
}
9911008

@@ -1000,6 +1017,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVIntegerType(
10001017
.addDef(createTypeVReg(CurMF->getRegInfo()))
10011018
.addImm(BitWidth)
10021019
.addImm(0);
1020+
DT.add(LLVMTy, CurMF, getSPIRVTypeID(MIB));
10031021
return finishCreatingSPIRVType(LLVMTy, MIB);
10041022
}
10051023

@@ -1020,6 +1038,7 @@ SPIRVGlobalRegistry::getOrCreateSPIRVBoolType(MachineInstr &I,
10201038
MachineBasicBlock &BB = *I.getParent();
10211039
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypeBool))
10221040
.addDef(createTypeVReg(CurMF->getRegInfo()));
1041+
DT.add(LLVMTy, CurMF, getSPIRVTypeID(MIB));
10231042
return finishCreatingSPIRVType(LLVMTy, MIB);
10241043
}
10251044

@@ -1044,6 +1063,7 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVVectorType(
10441063
.addDef(createTypeVReg(CurMF->getRegInfo()))
10451064
.addUse(getSPIRVTypeID(BaseType))
10461065
.addImm(NumElements);
1066+
DT.add(LLVMTy, CurMF, getSPIRVTypeID(MIB));
10471067
return finishCreatingSPIRVType(LLVMTy, MIB);
10481068
}
10491069

@@ -1062,32 +1082,46 @@ SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVArrayType(
10621082
.addDef(createTypeVReg(CurMF->getRegInfo()))
10631083
.addUse(getSPIRVTypeID(BaseType))
10641084
.addUse(Len);
1085+
DT.add(LLVMTy, CurMF, getSPIRVTypeID(MIB));
10651086
return finishCreatingSPIRVType(LLVMTy, MIB);
10661087
}
10671088

10681089
SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
10691090
SPIRVType *BaseType, MachineIRBuilder &MIRBuilder,
1070-
SPIRV::StorageClass::StorageClass SClass) {
1071-
return getOrCreateSPIRVType(
1072-
PointerType::get(const_cast<Type *>(getTypeForSPIRVType(BaseType)),
1073-
storageClassToAddressSpace(SClass)),
1074-
MIRBuilder);
1091+
SPIRV::StorageClass::StorageClass SC) {
1092+
const Type *PointerElementType = getTypeForSPIRVType(BaseType);
1093+
unsigned AddressSpace = storageClassToAddressSpace(SC);
1094+
Type *LLVMTy =
1095+
PointerType::get(const_cast<Type *>(PointerElementType), AddressSpace);
1096+
Register Reg = DT.find(PointerElementType, AddressSpace, CurMF);
1097+
if (Reg.isValid())
1098+
return getSPIRVTypeForVReg(Reg);
1099+
auto MIB = BuildMI(MIRBuilder.getMBB(), MIRBuilder.getInsertPt(),
1100+
MIRBuilder.getDebugLoc(),
1101+
MIRBuilder.getTII().get(SPIRV::OpTypePointer))
1102+
.addDef(createTypeVReg(CurMF->getRegInfo()))
1103+
.addImm(static_cast<uint32_t>(SC))
1104+
.addUse(getSPIRVTypeID(BaseType));
1105+
DT.add(PointerElementType, AddressSpace, CurMF, getSPIRVTypeID(MIB));
1106+
return finishCreatingSPIRVType(LLVMTy, MIB);
10751107
}
10761108

10771109
SPIRVType *SPIRVGlobalRegistry::getOrCreateSPIRVPointerType(
10781110
SPIRVType *BaseType, MachineInstr &I, const SPIRVInstrInfo &TII,
10791111
SPIRV::StorageClass::StorageClass SC) {
1112+
const Type *PointerElementType = getTypeForSPIRVType(BaseType);
1113+
unsigned AddressSpace = storageClassToAddressSpace(SC);
10801114
Type *LLVMTy =
1081-
PointerType::get(const_cast<Type *>(getTypeForSPIRVType(BaseType)),
1082-
storageClassToAddressSpace(SC));
1083-
Register Reg = DT.find(LLVMTy, CurMF);
1115+
PointerType::get(const_cast<Type *>(PointerElementType), AddressSpace);
1116+
Register Reg = DT.find(PointerElementType, AddressSpace, CurMF);
10841117
if (Reg.isValid())
10851118
return getSPIRVTypeForVReg(Reg);
10861119
MachineBasicBlock &BB = *I.getParent();
10871120
auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpTypePointer))
10881121
.addDef(createTypeVReg(CurMF->getRegInfo()))
10891122
.addImm(static_cast<uint32_t>(SC))
10901123
.addUse(getSPIRVTypeID(BaseType));
1124+
DT.add(PointerElementType, AddressSpace, CurMF, getSPIRVTypeID(MIB));
10911125
return finishCreatingSPIRVType(LLVMTy, MIB);
10921126
}
10931127

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1476,9 +1476,21 @@ bool SPIRVInstructionSelector::selectGlobalValue(
14761476
// FIXME: don't use MachineIRBuilder here, replace it with BuildMI.
14771477
MachineIRBuilder MIRBuilder(I);
14781478
const GlobalValue *GV = I.getOperand(1).getGlobal();
1479-
SPIRVType *ResType = GR.getOrCreateSPIRVType(
1480-
GV->getType(), MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false);
1481-
1479+
Type *GVType = GV->getValueType();
1480+
SPIRVType *PointerBaseType;
1481+
if (GVType->isArrayTy()) {
1482+
SPIRVType *ArrayElementType =
1483+
GR.getOrCreateSPIRVType(GVType->getArrayElementType(), MIRBuilder,
1484+
SPIRV::AccessQualifier::ReadWrite, false);
1485+
PointerBaseType = GR.getOrCreateSPIRVArrayType(
1486+
ArrayElementType, GVType->getArrayNumElements(), I, TII);
1487+
} else {
1488+
PointerBaseType = GR.getOrCreateSPIRVType(
1489+
GVType, MIRBuilder, SPIRV::AccessQualifier::ReadWrite, false);
1490+
}
1491+
SPIRVType *ResType = GR.getOrCreateSPIRVPointerType(
1492+
PointerBaseType, I, TII,
1493+
addressSpaceToStorageClass(GV->getAddressSpace()));
14821494
std::string GlobalIdent = GV->getGlobalIdentifier();
14831495
// We have functions as operands in tests with blocks of instruction e.g. in
14841496
// transcoding/global_block.ll. These operands are not used and should be
@@ -1489,8 +1501,6 @@ bool SPIRVInstructionSelector::selectGlobalValue(
14891501
MachineBasicBlock &BB = *I.getParent();
14901502
Register NewReg = GR.find(ConstVal, GR.CurMF);
14911503
if (!NewReg.isValid()) {
1492-
SPIRVType *SpvBaseTy = GR.getOrCreateSPIRVIntegerType(8, I, TII);
1493-
ResType = GR.getOrCreateSPIRVPointerType(SpvBaseTy, I, TII);
14941504
Register NewReg = ResVReg;
14951505
GR.add(ConstVal, GR.CurMF, NewReg);
14961506
return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull))

‎llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -242,7 +242,19 @@ static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
242242
!ReachedBegin;) {
243243
MachineInstr &MI = *MII;
244244

245-
if (isSpvIntrinsic(MI, Intrinsic::spv_assign_type)) {
245+
if (isSpvIntrinsic(MI, Intrinsic::spv_assign_ptr_type)) {
246+
Register Reg = MI.getOperand(1).getReg();
247+
MIB.setInsertPt(*MI.getParent(), MI.getIterator());
248+
SPIRVType *BaseTy = GR->getOrCreateSPIRVType(
249+
getMDOperandAsType(MI.getOperand(2).getMetadata(), 0), MIB);
250+
SPIRVType *AssignedPtrType = GR->getOrCreateSPIRVPointerType(
251+
BaseTy, MI, *MF.getSubtarget<SPIRVSubtarget>().getInstrInfo());
252+
MachineInstr *Def = MRI.getVRegDef(Reg);
253+
assert(Def && "Expecting an instruction that defines the register");
254+
insertAssignInstr(Reg, nullptr, AssignedPtrType, GR, MIB,
255+
MF.getRegInfo());
256+
ToErase.push_back(&MI);
257+
} else if (isSpvIntrinsic(MI, Intrinsic::spv_assign_type)) {
246258
Register Reg = MI.getOperand(1).getReg();
247259
Type *Ty = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0);
248260
MachineInstr *Def = MRI.getVRegDef(Reg);

‎llvm/test/CodeGen/SPIRV/EnqueueEmptyKernel.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
1+
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
22

33
;; This test checks that Invoke parameter of OpEnueueKernel instruction meet the
44
;; following specification requirements in case of enqueueing empty block:

‎llvm/test/CodeGen/SPIRV/SampledImageRetType.ll

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,24 @@
1-
; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
1+
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
22

3-
%opencl.image1d_ro_t = type opaque
43
; CHECK: %[[#image1d_t:]] = OpTypeImage
5-
%opencl.sampler_t = type opaque
64
; CHECK: %[[#sampler_t:]] = OpTypeSampler
75
; CHECK: %[[#sampled_image_t:]] = OpTypeSampledImage
86

9-
declare dso_local spir_func i8 addrspace(4)* @_Z20__spirv_SampledImageI14ocl_image1d_roPvET0_T_11ocl_sampler(%opencl.image1d_ro_t addrspace(1)*, %opencl.sampler_t addrspace(2)*) local_unnamed_addr
7+
declare dso_local spir_func ptr addrspace(4) @_Z20__spirv_SampledImageI14ocl_image1d_roPvET0_T_11ocl_sampler(target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 0) %0, target("spirv.Sampler") %1) local_unnamed_addr
108

11-
declare dso_local spir_func <4 x float> @_Z30__spirv_ImageSampleExplicitLodIPvDv4_fiET0_T_T1_if(i8 addrspace(4)*, i32, i32, float) local_unnamed_addr
9+
declare dso_local spir_func <4 x float> @_Z30__spirv_ImageSampleExplicitLodIPvDv4_fiET0_T_T1_if(ptr addrspace(4) %0, i32 %1, i32 %2, float %3) local_unnamed_addr
1210

1311
@__spirv_BuiltInGlobalInvocationId = external dso_local local_unnamed_addr addrspace(2) constant <3 x i64>, align 32
1412

15-
define weak_odr dso_local spir_kernel void @_ZTS17image_kernel_readILi1EE(%opencl.image1d_ro_t addrspace(1)*, %opencl.sampler_t addrspace(2)*) {
13+
define weak_odr dso_local spir_kernel void @_ZTS17image_kernel_readILi1EE(target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 0), target("spirv.Sampler")) {
1614
; CHECK: OpFunction
1715
; CHECK: %[[#image:]] = OpFunctionParameter %[[#image1d_t]]
1816
; CHECK: %[[#sampler:]] = OpFunctionParameter %[[#sampler_t]]
19-
%3 = load <3 x i64>, <3 x i64> addrspace(2)* @__spirv_BuiltInGlobalInvocationId, align 32
17+
%3 = load <3 x i64>, ptr addrspace(2) @__spirv_BuiltInGlobalInvocationId, align 32
2018
%4 = extractelement <3 x i64> %3, i64 0
2119
%5 = trunc i64 %4 to i32
22-
%6 = tail call spir_func i8 addrspace(4)* @_Z20__spirv_SampledImageI14ocl_image1d_roPvET0_T_11ocl_sampler(%opencl.image1d_ro_t addrspace(1)* %0, %opencl.sampler_t addrspace(2)* %1)
23-
%7 = tail call spir_func <4 x float> @_Z30__spirv_ImageSampleExplicitLodIPvDv4_fiET0_T_T1_if(i8 addrspace(4)* %6, i32 %5, i32 2, float 0.000000e+00)
20+
%6 = call spir_func ptr addrspace(4) @_Z20__spirv_SampledImageI14ocl_image1d_roPvET0_T_11ocl_sampler(target("spirv.Image", void, 0, 0, 0, 0, 0, 0, 0) %0, target("spirv.Sampler") %1)
21+
%7 = call spir_func <4 x float> @_Z30__spirv_ImageSampleExplicitLodIPvDv4_fiET0_T_T1_if(ptr addrspace(4) %6, i32 %5, i32 2, float 0.000000e+00)
2422

2523
; CHECK: %[[#sampled_image:]] = OpSampledImage %[[#sampled_image_t]] %[[#image]] %[[#sampler]]
2624
; CHECK: %[[#]] = OpImageSampleExplicitLod %[[#]] %[[#sampled_image]] %[[#]] {{.*}} %[[#]]

‎llvm/test/CodeGen/SPIRV/atomicrmw.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
1+
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
22

33
; CHECK: %[[#Int:]] = OpTypeInt 32 0
44
; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1 {{$}}

‎llvm/test/CodeGen/SPIRV/constant/global-constants.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
1+
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
22

33
@global = addrspace(1) constant i32 1 ; OpenCL global memory
44
@constant = addrspace(2) constant i32 2 ; OpenCL constant memory

‎llvm/test/CodeGen/SPIRV/constant/local-null-constants.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,21 @@
1-
; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
1+
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
22

33
;; OpenCL global memory
4-
define i32 addrspace(1)* @getConstant1() {
5-
ret i32 addrspace(1)* null
4+
define ptr addrspace(1) @getConstant1() {
5+
ret ptr addrspace(1) null
66
}
77

88
;; OpenCL constant memory
9-
define i32 addrspace(2)* @getConstant2() {
10-
ret i32 addrspace(2)* null
9+
define ptr addrspace(2) @getConstant2() {
10+
ret ptr addrspace(2) null
1111
}
1212

1313
;; OpenCL local memory
14-
define i32 addrspace(3)* @getConstant3() {
15-
ret i32 addrspace(3)* null
14+
define ptr addrspace(3) @getConstant3() {
15+
ret ptr addrspace(3) null
1616
}
1717

18-
; CHECK: [[INT:%.+]] = OpTypeInt 32
18+
; CHECK: [[INT:%.+]] = OpTypeInt 8
1919

2020
; CHECK-DAG: [[PTR_AS1:%.+]] = OpTypePointer CrossWorkgroup [[INT]]
2121
; CHECK-DAG: OpConstantNull [[PTR_AS1]]

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