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[Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled
This commit updates the Hexagon backend to handle vxi1 call operands Without HVX enabled. It ensures compatibility for vector types of sizes 4, 8, 16, 32, 64, and 128 x i1 when HVX is not enabled. Change-Id: Iddecb58b7e2884cc7b3b35569c0768e203979e95
1 parent b6820c3 commit edbbc39

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6 files changed

+138
-17
lines changed

6 files changed

+138
-17
lines changed

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,84 @@ static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
155155
}
156156

157157
#include "HexagonGenCallingConv.inc"
158+
unsigned HexagonTargetLowering::getVectorTypeBreakdownForCallingConv(
159+
LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
160+
unsigned &NumIntermediates, MVT &RegisterVT) const {
161+
162+
RegisterVT = MVT::v8i8;
163+
IntermediateVT = MVT::v8i1;
164+
// Split vectors of type vXi1 into (X/8) vectors of type v8i1,
165+
// where X is divisible by 8.
166+
if (!Subtarget.useHVXOps()) {
167+
switch (VT.getSimpleVT().SimpleTy) {
168+
case MVT::v16i1:
169+
NumIntermediates = 2;
170+
return 2;
171+
case MVT::v32i1:
172+
NumIntermediates = 4;
173+
return 4;
174+
case MVT::v64i1:
175+
NumIntermediates = 8;
176+
return 8;
177+
case MVT::v128i1:
178+
NumIntermediates = 16;
179+
return 16;
180+
default:
181+
break;
182+
}
183+
}
184+
// Split v128i1 vectors into 2 v64i1 vectors in HVX 64-byte mode.
185+
if (VT == MVT::v128i1 && Subtarget.useHVX64BOps()) {
186+
RegisterVT = MVT::v64i8;
187+
IntermediateVT = MVT::v64i1;
188+
NumIntermediates = 2;
189+
return 2;
190+
}
191+
return TargetLowering::getVectorTypeBreakdownForCallingConv(
192+
Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
193+
}
194+
std::pair<MVT, unsigned>
195+
HexagonTargetLowering::handleMaskRegisterForCallingConv(
196+
unsigned NumElts, CallingConv::ID CC, const HexagonSubtarget &Subtarget,
197+
EVT VT) const {
198+
199+
unsigned NumIntermediates = 1;
200+
ElementCount EC = VT.getVectorElementCount();
201+
// For vectors of type vXi1, where X is divisible by 8,
202+
// use Double registers when HVX is not enabled.
203+
if (VT.getVectorNumElements() >= 16 && !Subtarget.useHVXOps() &&
204+
isPowerOf2_32(EC.getKnownMinValue())) {
205+
while (EC.getKnownMinValue() > 8) {
206+
EC = EC.divideCoefficientBy(2);
207+
208+
NumIntermediates <<= 1;
209+
}
210+
return {MVT::v8i8, NumIntermediates};
211+
}
212+
// Split v128i1 vectors into 2 v64i1 vectors in HVX 64-byte mode.
213+
if (VT == MVT::v128i1 && Subtarget.useHVX64BOps()) {
214+
return {MVT::v64i8, 2};
215+
}
216+
return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
217+
}
218+
219+
MVT HexagonTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
220+
CallingConv::ID CC,
221+
EVT VT) const {
222+
if (VT.isVector()) {
223+
if (VT.getVectorElementType() == MVT::i1) {
224+
unsigned NumElts = VT.getVectorNumElements();
158225

226+
MVT RegisterVT;
227+
unsigned NumRegisters;
228+
std::tie(RegisterVT, NumRegisters) =
229+
handleMaskRegisterForCallingConv(NumElts, CC, Subtarget, VT);
230+
if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
231+
return RegisterVT;
232+
}
233+
}
234+
return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
235+
}
159236

160237
SDValue
161238
HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)

‎llvm/lib/Target/Hexagon/HexagonISelLowering.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,10 @@ class HexagonTargetLowering : public TargetLowering {
183183
SelectionDAG &DAG) const override;
184184

185185
const char *getTargetNodeName(unsigned Opcode) const override;
186+
std::pair<MVT, unsigned>
187+
handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
188+
const HexagonSubtarget &Subtarget,
189+
EVT VT) const;
186190

187191
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
188192
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
@@ -263,6 +267,14 @@ class HexagonTargetLowering : public TargetLowering {
263267
Register getRegisterByName(const char* RegName, LLT VT,
264268
const MachineFunction &MF) const override;
265269

270+
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context,
271+
CallingConv::ID CC, EVT VT,
272+
EVT &IntermediateVT,
273+
unsigned &NumIntermediates,
274+
MVT &RegisterVT) const override;
275+
276+
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC,
277+
EVT VT) const override;
266278
/// If a physical register, this returns the register that receives the
267279
/// exception address on entry to an EH pad.
268280
Register

‎llvm/test/CodeGen/Hexagon/calloperand-v128i1.ll

Lines changed: 21 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,20 @@
1-
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s
1+
;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
2+
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefixes=CHECK-64,CHECK-64-128
3+
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefixes=CHECK-128,CHECK-64-128
24

35
; CHECK-LABEL: compare_vectors
4-
; CHECK: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
5-
; CHECK: [[REG2:(r[0-9]+)]] = #-1
6-
; CHECK: v0 = vand([[REG1]],[[REG2]])
7-
6+
; CHECK: [[REG8:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
7+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
8+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
9+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
10+
; CHECK-128: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
11+
; CHECK-128: [[REG2:(r[0-9]+)]] = #-1
12+
; CHECK-128: v0 = vand([[REG1]],[[REG2]])
13+
; CHECK-64: [[REG5:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
14+
; CHECK-64: [[REG6:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
15+
; CHECK-64: [[REG7:(r[0-9]+)]] = #-1
16+
; CHECK-64: v0 = vand([[REG5]],[[REG7]])
17+
; CHECK-64: v1 = vand([[REG6]],[[REG7]])
818
define void @compare_vectors(<128 x i8> %a, <128 x i8> %b) {
919
entry:
1020
%result = icmp eq <128 x i8> %a, %b
@@ -13,11 +23,13 @@ entry:
1323
}
1424

1525
; CHECK-LABEL: f.1:
16-
; CHECK: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
17-
; CHECK: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
18-
; CHECK: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
26+
; CHECK: [[REG9:(r[0-9]+)]] = and([[REG9]],##16843009)
27+
; CHECK: [[REG10:(r[0-9]+)]] = and([[REG10]],##16843009)
28+
; CHECK-64-128: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
29+
; CHECK-64-128: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
30+
; CHECK-64-128: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
1931

20-
define i32 @f.1(<128 x i1> %vec) {
32+
define i32 @f.1(<128 x i1> %vec){
2133
%element = extractelement <128 x i1> %vec, i32 6
2234
%is_true = icmp eq i1 %element, true
2335
br i1 %is_true, label %if_true, label %if_false

‎llvm/test/CodeGen/Hexagon/calloperand-v16i1.ll

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,15 @@
1-
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK
2-
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK
1+
;RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
2+
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-HVX
3+
;RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-HVX
34

45
; CHECK-LABEL: compare_vectors
5-
; CHECK: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
6-
; CHECK: [[REG2:(r[0-9]+)]] = #-1
7-
; CHECK: v0 = vand([[REG1]],[[REG2]])
6+
; CHECK: [[REG5:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
7+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG5]])
8+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG5]])
9+
10+
; CHECK-HVX: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.w,v{{[0-9]+}}.w)
11+
; CHECK-HVX: [[REG2:(r[0-9]+)]] = #-1
12+
; CHECK-HVX: v0 = vand([[REG1]],[[REG2]])
813

914
define void @compare_vectors(<16 x i32> %a, <16 x i32> %b) {
1015
entry:
@@ -14,9 +19,11 @@ entry:
1419
}
1520

1621
; CHECK-LABEL: f.1:
17-
; CHECK: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
18-
; CHECK: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
19-
; CHECK: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
22+
; CHECK: [[REG3:(r[0-9]+)]] = and([[REG3]],##16843009)
23+
; CHECK: [[REG4:(r[0-9]+)]] = and([[REG4]],##16843009)
24+
; CHECK-HVX: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
25+
; CHECK-HVX: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
26+
; CHECK-HVX: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})
2027

2128
define i32 @f.1(<16 x i1> %vec) {
2229
%element = extractelement <16 x i1> %vec, i32 6

‎llvm/test/CodeGen/Hexagon/calloperand-v32i1.ll

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,11 @@
1+
; RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
12
; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-64
23
; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-128
34

45
; CHECK-LABEL: compare_vectors
6+
; CHECK: [[REG8:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
7+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
8+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
59
; CHECK-64: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
610
; CHECK-64: [[REG2:(r[0-9]+)]] = #-1
711
; CHECK-64: v0 = vand([[REG1]],[[REG2]])
@@ -21,6 +25,8 @@ entry:
2125
}
2226

2327
; CHECK-LABEL: f.1:
28+
; CHECK: [[REG9:(r[0-9]+)]] = and([[REG9]],##16843009)
29+
; CHECK: [[REG10:(r[0-9]+)]] = and([[REG10]],##16843009)
2430
; CHECK-64: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
2531
; CHECK-64: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
2632
; CHECK-64: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})

‎llvm/test/CodeGen/Hexagon/calloperand-v64i1.ll

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,12 @@
1+
; RUN: llc -mtriple=hexagon < %s -o - | FileCheck %s --check-prefix=CHECK
12
; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length64b < %s -o - | FileCheck %s --check-prefix=CHECK-64
23
; RUN: llc -mtriple=hexagon -mattr=+hvxv79,+hvx-length128b < %s -o - | FileCheck %s --check-prefix=CHECK-128
34

45
; CHECK-LABEL: compare_vectors
6+
; CHECK: [[REG8:(r[0-9]+):[0-9]]] = CONST64(#72340172838076673)
7+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
8+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
9+
; CHECK: r{{[0-9]+}}:{{[0-9]+}} = and(r{{[0-9]+}}:{{[0-9]+}},[[REG8]])
510
; CHECK-64: [[REG1:(q[0-9]+)]] = vcmp.eq(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
611
; CHECK-64: [[REG2:(r[0-9]+)]] = #-1
712
; CHECK-64: v0 = vand([[REG1]],[[REG2]])
@@ -21,6 +26,8 @@ entry:
2126
}
2227

2328
; CHECK-LABEL: f.1:
29+
; CHECK: [[REG9:(r[0-9]+)]] = and([[REG9]],##16843009)
30+
; CHECK: [[REG10:(r[0-9]+)]] = and([[REG10]],##16843009)
2431
; CHECK-64: [[REG3:(q[0-9]+)]] = vand(v0,r{{[0-9]+}})
2532
; CHECK-64: [[REG4:(v[0-9]+)]] = vand([[REG3]],r{{[0-9]+}})
2633
; CHECK-64: r{{[0-9]+}} = vextract([[REG4]],r{{[0-9]+}})

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