@@ -2955,10 +2955,6 @@ static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
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if (SatVT != DstEltVT)
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return SDValue();
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- // FIXME: Don't support narrowing by more than 1 steps for now.
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- if (SrcEltSize > (2 * DstEltSize))
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- return SDValue();
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-
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MVT DstContainerVT = DstVT;
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MVT SrcContainerVT = SrcVT;
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if (DstVT.isFixedLengthVector()) {
@@ -2986,9 +2982,29 @@ static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
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Src = DAG.getNode(RISCVISD::FP_EXTEND_VL, DL, InterVT, Src, Mask, VL);
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}
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+ MVT CvtContainerVT = DstContainerVT;
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+ MVT CvtEltVT = DstEltVT;
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+ if (SrcEltSize > (2 * DstEltSize)) {
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+ CvtEltVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits() / 2);
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+ CvtContainerVT = CvtContainerVT.changeVectorElementType(CvtEltVT);
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+ }
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+
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unsigned RVVOpc =
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IsSigned ? RISCVISD::VFCVT_RTZ_X_F_VL : RISCVISD::VFCVT_RTZ_XU_F_VL;
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- SDValue Res = DAG.getNode(RVVOpc, DL, DstContainerVT, Src, Mask, VL);
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+ SDValue Res = DAG.getNode(RVVOpc, DL, CvtContainerVT, Src, Mask, VL);
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+
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+ while (CvtContainerVT != DstContainerVT) {
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+ CvtEltVT = MVT::getIntegerVT(CvtEltVT.getSizeInBits() / 2);
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+ CvtContainerVT = CvtContainerVT.changeVectorElementType(CvtEltVT);
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+ // Rounding mode here is arbitrary since we aren't shifting out any bits.
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+ unsigned ClipOpc = IsSigned ? RISCVISD::VNCLIP_VL : RISCVISD::VNCLIPU_VL;
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+ Res = DAG.getNode(
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+ ClipOpc, DL, CvtContainerVT,
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+ {Res, DAG.getConstant(0, DL, CvtContainerVT),
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+ DAG.getUNDEF(CvtContainerVT), Mask,
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+ DAG.getTargetConstant(RISCVVXRndMode::RNU, DL, Subtarget.getXLenVT()),
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+ VL});
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+ }
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SDValue SplatZero = DAG.getNode(
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RISCVISD::VMV_V_X_VL, DL, DstContainerVT, DAG.getUNDEF(DstContainerVT),
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