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[AArch64][TargetParser] move CPUInfo into tablegen [NFC] (#92145)
This is a follow up to #92037, which moved the architecture information. Generate the AArch64TargetParser CPUInfo from tablegen Processor defs using a new tablegen emitter. Some basic error checking is added in the emitter to ensure that duplicate features are not added to the Processor defs. The generic CPU becomes an entry in tablegen. Some CPU features which were present in the CPUInfo but absent from the tablegen defs have been added to tablegen. FeatureCrypto is replaced with FeatureSHA2 and FeatureAES. This changes a few of the tests.
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-668
lines changed

11 files changed

+576
-668
lines changed

‎clang/lib/Basic/Targets/AArch64.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -258,7 +258,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef,
258258
}
259259

260260
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
261-
return Name == "generic" || llvm::AArch64::parseCpu(Name);
261+
return llvm::AArch64::parseCpu(Name).has_value();
262262
}
263263

264264
bool AArch64TargetInfo::setCPU(const std::string &Name) {

‎clang/lib/Driver/ToolChains/Arch/AArch64.cpp

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -98,16 +98,12 @@ static bool DecodeAArch64Mcpu(const Driver &D, StringRef Mcpu, StringRef &CPU,
9898
if (CPU == "native")
9999
CPU = llvm::sys::getHostCPUName();
100100

101-
if (CPU == "generic") {
102-
Extensions.enable(llvm::AArch64::AEK_SIMD);
103-
} else {
104-
const std::optional<llvm::AArch64::CpuInfo> CpuInfo =
105-
llvm::AArch64::parseCpu(CPU);
106-
if (!CpuInfo)
107-
return false;
101+
const std::optional<llvm::AArch64::CpuInfo> CpuInfo =
102+
llvm::AArch64::parseCpu(CPU);
103+
if (!CpuInfo)
104+
return false;
108105

109-
Extensions.addCPUDefaults(*CpuInfo);
110-
}
106+
Extensions.addCPUDefaults(*CpuInfo);
111107

112108
if (Split.second.size() &&
113109
!DecodeAArch64Features(D, Split.second, Extensions))

‎clang/test/CodeGen/aarch64-targetattr.c

Lines changed: 165 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1,115 +1,232 @@
1-
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals
22
// RUN: %clang_cc1 -triple aarch64 -emit-llvm %s -o - | FileCheck %s
33

4-
// CHECK-LABEL: @v82() #0
54
__attribute__((target("arch=armv8.2-a")))
5+
// CHECK-LABEL: define {{[^@]+}}@v82
6+
// CHECK-SAME: () #[[ATTR0:[0-9]+]] {
7+
// CHECK-NEXT: entry:
8+
// CHECK-NEXT: ret void
9+
//
610
void v82() {}
7-
// CHECK-LABEL: @v82sve() #1
811
__attribute__((target("arch=armv8.2-a+sve")))
12+
// CHECK-LABEL: define {{[^@]+}}@v82sve
13+
// CHECK-SAME: () #[[ATTR1:[0-9]+]] {
14+
// CHECK-NEXT: entry:
15+
// CHECK-NEXT: ret void
16+
//
917
void v82sve() {}
10-
// CHECK-LABEL: @v82sve2() #2
1118
__attribute__((target("arch=armv8.2-a+sve2")))
19+
// CHECK-LABEL: define {{[^@]+}}@v82sve2
20+
// CHECK-SAME: () #[[ATTR2:[0-9]+]] {
21+
// CHECK-NEXT: entry:
22+
// CHECK-NEXT: ret void
23+
//
1224
void v82sve2() {}
13-
// CHECK-LABEL: @v82svesve2() #2
1425
__attribute__((target("arch=armv8.2-a+sve+sve2")))
26+
// CHECK-LABEL: define {{[^@]+}}@v82svesve2
27+
// CHECK-SAME: () #[[ATTR2]] {
28+
// CHECK-NEXT: entry:
29+
// CHECK-NEXT: ret void
30+
//
1531
void v82svesve2() {}
16-
// CHECK-LABEL: @v86sve2() #3
1732
__attribute__((target("arch=armv8.6-a+sve2")))
33+
// CHECK-LABEL: define {{[^@]+}}@v86sve2
34+
// CHECK-SAME: () #[[ATTR3:[0-9]+]] {
35+
// CHECK-NEXT: entry:
36+
// CHECK-NEXT: ret void
37+
//
1838
void v86sve2() {}
1939

20-
// CHECK-LABEL: @a710() #4
2140
__attribute__((target("cpu=cortex-a710")))
41+
// CHECK-LABEL: define {{[^@]+}}@a710
42+
// CHECK-SAME: () #[[ATTR4:[0-9]+]] {
43+
// CHECK-NEXT: entry:
44+
// CHECK-NEXT: ret void
45+
//
2246
void a710() {}
23-
// CHECK-LABEL: @tunea710() #5
2447
__attribute__((target("tune=cortex-a710")))
48+
// CHECK-LABEL: define {{[^@]+}}@tunea710
49+
// CHECK-SAME: () #[[ATTR5:[0-9]+]] {
50+
// CHECK-NEXT: entry:
51+
// CHECK-NEXT: ret void
52+
//
2553
void tunea710() {}
26-
// CHECK-LABEL: @generic() #6
2754
__attribute__((target("cpu=generic")))
55+
// CHECK-LABEL: define {{[^@]+}}@generic
56+
// CHECK-SAME: () #[[ATTR6:[0-9]+]] {
57+
// CHECK-NEXT: entry:
58+
// CHECK-NEXT: ret void
59+
//
2860
void generic() {}
29-
// CHECK-LABEL: @tune() #7
3061
__attribute__((target("tune=generic")))
62+
// CHECK-LABEL: define {{[^@]+}}@tune
63+
// CHECK-SAME: () #[[ATTR7:[0-9]+]] {
64+
// CHECK-NEXT: entry:
65+
// CHECK-NEXT: ret void
66+
//
3167
void tune() {}
3268

33-
// CHECK-LABEL: @n1tunea710() #8
3469
__attribute__((target("cpu=neoverse-n1,tune=cortex-a710")))
70+
// CHECK-LABEL: define {{[^@]+}}@n1tunea710
71+
// CHECK-SAME: () #[[ATTR8:[0-9]+]] {
72+
// CHECK-NEXT: entry:
73+
// CHECK-NEXT: ret void
74+
//
3575
void n1tunea710() {}
36-
// CHECK-LABEL: @svetunea710() #9
3776
__attribute__((target("sve,tune=cortex-a710")))
77+
// CHECK-LABEL: define {{[^@]+}}@svetunea710
78+
// CHECK-SAME: () #[[ATTR9:[0-9]+]] {
79+
// CHECK-NEXT: entry:
80+
// CHECK-NEXT: ret void
81+
//
3882
void svetunea710() {}
39-
// CHECK-LABEL: @plussvetunea710() #9
4083
__attribute__((target("+sve,tune=cortex-a710")))
84+
// CHECK-LABEL: define {{[^@]+}}@plussvetunea710
85+
// CHECK-SAME: () #[[ATTR9]] {
86+
// CHECK-NEXT: entry:
87+
// CHECK-NEXT: ret void
88+
//
4189
void plussvetunea710() {}
42-
// CHECK-LABEL: @v1plussve2() #10
4390
__attribute__((target("cpu=neoverse-v1,+sve2")))
91+
// CHECK-LABEL: define {{[^@]+}}@v1plussve2
92+
// CHECK-SAME: () #[[ATTR10:[0-9]+]] {
93+
// CHECK-NEXT: entry:
94+
// CHECK-NEXT: ret void
95+
//
4496
void v1plussve2() {}
45-
// CHECK-LABEL: @v1sve2() #10
4697
__attribute__((target("cpu=neoverse-v1+sve2")))
98+
// CHECK-LABEL: define {{[^@]+}}@v1sve2
99+
// CHECK-SAME: () #[[ATTR10]] {
100+
// CHECK-NEXT: entry:
101+
// CHECK-NEXT: ret void
102+
//
47103
void v1sve2() {}
48-
// CHECK-LABEL: @v1minussve() #11
49104
__attribute__((target("cpu=neoverse-v1,+nosve")))
105+
// CHECK-LABEL: define {{[^@]+}}@v1minussve
106+
// CHECK-SAME: () #[[ATTR11:[0-9]+]] {
107+
// CHECK-NEXT: entry:
108+
// CHECK-NEXT: ret void
109+
//
50110
void v1minussve() {}
51-
// CHECK-LABEL: @v1nosve() #11
52111
__attribute__((target("cpu=neoverse-v1,no-sve")))
112+
// CHECK-LABEL: define {{[^@]+}}@v1nosve
113+
// CHECK-SAME: () #[[ATTR11]] {
114+
// CHECK-NEXT: entry:
115+
// CHECK-NEXT: ret void
116+
//
53117
void v1nosve() {}
54-
// CHECK-LABEL: @v1msve() #11
55118
__attribute__((target("cpu=neoverse-v1+nosve")))
119+
// CHECK-LABEL: define {{[^@]+}}@v1msve
120+
// CHECK-SAME: () #[[ATTR11]] {
121+
// CHECK-NEXT: entry:
122+
// CHECK-NEXT: ret void
123+
//
56124
void v1msve() {}
57125

58-
// CHECK-LABEL: @plussve() #12
59126
__attribute__((target("+sve")))
127+
// CHECK-LABEL: define {{[^@]+}}@plussve
128+
// CHECK-SAME: () #[[ATTR12:[0-9]+]] {
129+
// CHECK-NEXT: entry:
130+
// CHECK-NEXT: ret void
131+
//
60132
void plussve() {}
61-
// CHECK-LABEL: @plussveplussve2() #13
62133
__attribute__((target("+sve+nosve2")))
134+
// CHECK-LABEL: define {{[^@]+}}@plussveplussve2
135+
// CHECK-SAME: () #[[ATTR13:[0-9]+]] {
136+
// CHECK-NEXT: entry:
137+
// CHECK-NEXT: ret void
138+
//
63139
void plussveplussve2() {}
64-
// CHECK-LABEL: @plussveminusnosve2() #13
65140
__attribute__((target("sve,no-sve2")))
141+
// CHECK-LABEL: define {{[^@]+}}@plussveminusnosve2
142+
// CHECK-SAME: () #[[ATTR13]] {
143+
// CHECK-NEXT: entry:
144+
// CHECK-NEXT: ret void
145+
//
66146
void plussveminusnosve2() {}
67-
// CHECK-LABEL: @plusfp16() #14
68147
__attribute__((target("+fp16")))
148+
// CHECK-LABEL: define {{[^@]+}}@plusfp16
149+
// CHECK-SAME: () #[[ATTR14:[0-9]+]] {
150+
// CHECK-NEXT: entry:
151+
// CHECK-NEXT: ret void
152+
//
69153
void plusfp16() {}
70154

71-
// CHECK-LABEL: @all() #15
72155
__attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2")))
156+
// CHECK-LABEL: define {{[^@]+}}@all
157+
// CHECK-SAME: () #[[ATTR15:[0-9]+]] {
158+
// CHECK-NEXT: entry:
159+
// CHECK-NEXT: ret void
160+
//
73161
void all() {}
74-
// CHECK-LABEL: @allplusbranchprotection() #16
75162
__attribute__((target("cpu=neoverse-n1,tune=cortex-a710,arch=armv8.6-a+sve2,branch-protection=standard")))
163+
// CHECK-LABEL: define {{[^@]+}}@allplusbranchprotection
164+
// CHECK-SAME: () #[[ATTR16:[0-9]+]] {
165+
// CHECK-NEXT: entry:
166+
// CHECK-NEXT: ret void
167+
//
76168
void allplusbranchprotection() {}
77169

78170
// These tests check that the user facing and internal llvm name are both accepted.
79-
// CHECK-LABEL: @plusnoneon() #17
80171
__attribute__((target("+noneon")))
172+
// CHECK-LABEL: define {{[^@]+}}@plusnoneon
173+
// CHECK-SAME: () #[[ATTR17:[0-9]+]] {
174+
// CHECK-NEXT: entry:
175+
// CHECK-NEXT: ret void
176+
//
81177
void plusnoneon() {}
82-
// CHECK-LABEL: @plusnosimd() #17
83178
__attribute__((target("+nosimd")))
179+
// CHECK-LABEL: define {{[^@]+}}@plusnosimd
180+
// CHECK-SAME: () #[[ATTR17]] {
181+
// CHECK-NEXT: entry:
182+
// CHECK-NEXT: ret void
183+
//
84184
void plusnosimd() {}
85-
// CHECK-LABEL: @noneon() #17
86185
__attribute__((target("no-neon")))
186+
// CHECK-LABEL: define {{[^@]+}}@noneon
187+
// CHECK-SAME: () #[[ATTR17]] {
188+
// CHECK-NEXT: entry:
189+
// CHECK-NEXT: ret void
190+
//
87191
void noneon() {}
88-
// CHECK-LABEL: @nosimd() #17
89192
__attribute__((target("no-simd")))
193+
// CHECK-LABEL: define {{[^@]+}}@nosimd
194+
// CHECK-SAME: () #[[ATTR17]] {
195+
// CHECK-NEXT: entry:
196+
// CHECK-NEXT: ret void
197+
//
90198
void nosimd() {}
91199

92200
// This isn't part of the standard interface, but test that -arch features should not apply anything else.
93-
// CHECK-LABEL: @minusarch() #18
94201
__attribute__((target("no-v9.3a")))
202+
// CHECK-LABEL: define {{[^@]+}}@minusarch
203+
// CHECK-SAME: () #[[ATTR18:[0-9]+]] {
204+
// CHECK-NEXT: entry:
205+
// CHECK-NEXT: ret void
206+
//
95207
void minusarch() {}
96208

97-
// CHECK: attributes #0 = { {{.*}} "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
98-
// CHECK: attributes #1 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
99-
// CHECK: attributes #2 = { {{.*}} "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
100-
// CHECK: attributes #3 = { {{.*}} "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
101-
// CHECK: attributes #4 = { {{.*}} "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" }
102-
// CHECK: attributes #5 = { {{.*}} "tune-cpu"="cortex-a710" }
103-
// CHECK: attributes #6 = { {{.*}} "target-cpu"="generic" }
104-
// CHECK: attributes #7 = { {{.*}} "tune-cpu"="generic" }
105-
// CHECK: attributes #8 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs" "tune-cpu"="cortex-a710" }
106-
// CHECK: attributes #9 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" }
107-
// CHECK: attributes #10 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2" }
108-
// CHECK: attributes #11 = { {{.*}} "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve" }
109-
// CHECK: attributes #12 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
110-
// CHECK: attributes #13 = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" }
111-
// CHECK: attributes #14 = { {{.*}} "target-features"="+fullfp16" }
112-
// CHECK: attributes #15 = { {{.*}} "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
113-
// CHECK: attributes #16 = { {{.*}} "branch-target-enforcement"="true" "guarded-control-stack"="true" {{.*}} "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
114-
// CHECK: attributes #17 = { {{.*}} "target-features"="-neon" }
115-
// CHECK: attributes #18 = { {{.*}} "target-features"="-v9.3a" }
209+
//.
210+
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+lse,+neon,+ras,+rdm,+v8.1a,+v8.2a,+v8a" }
211+
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+v8.1a,+v8.2a,+v8a" }
212+
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+crc,+fp-armv8,+fullfp16,+lse,+neon,+ras,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8a" }
213+
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+ras,+rcpc,+rdm,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" }
214+
// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-a710" "target-features"="+bf16,+complxnum,+crc,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+mte,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sb,+sve,+sve2,+sve2-bitperm" }
215+
// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="cortex-a710" }
216+
// CHECK: attributes #[[ATTR6]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon" }
217+
// CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" }
218+
// CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs" "tune-cpu"="cortex-a710" }
219+
// CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve" "tune-cpu"="cortex-a710" }
220+
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2" }
221+
// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,-sve" }
222+
// CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve" }
223+
// CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,-sve2" }
224+
// CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fullfp16" }
225+
// CHECK: attributes #[[ATTR15]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
226+
// CHECK: attributes #[[ATTR16]] = { noinline nounwind optnone "branch-protection-pauth-lr"="false" "branch-target-enforcement"="true" "guarded-control-stack"="true" "no-trapping-math"="true" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+complxnum,+crc,+dotprod,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" }
227+
// CHECK: attributes #[[ATTR17]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-neon" }
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// CHECK: attributes #[[ATTR18]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="-v9.3a" }
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//.
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// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
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// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
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//.

‎clang/test/Misc/target-invalid-cpu-note.c

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66
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
77
// AARCH64: error: unknown target CPU 'not-a-cpu'
8-
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-m4, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
8+
// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35, cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4, apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16, apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
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// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
1111
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
12-
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-m4, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
12+
// TUNE_AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35, cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4, apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16, apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
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// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
1515
// X86: error: unknown target CPU 'not-a-cpu'

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