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[AMDGPU][Attributor] Make AAAMDFlatWorkGroupSize honor existing attribute
If a function has `amdgpu-flat-work-group-size`, honor it in `initialize` by taking its value directly; otherwise, it uses the default range as a starting point. We will no longer manipulatethe known range, which can cause issues because the known range is a "throttle" to the assumed range such that the assumed range can't get widened properly in `updateImpl` if the known range is not set properly for whatever reasons. Another benefit of not touching the known range is, if we indicate pessimistic state, it also invalidates the AA such that `manifest` will not be called. Since we honor the attribute, we don't want and will not add any half-baked attribute added to a function.
1 parent fe52152 commit f1aea50

25 files changed

+323
-256
lines changed

llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

Lines changed: 70 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,20 @@ static bool funcRequiresHostcallPtr(const Function &F) {
144144
}
145145

146146
namespace {
147+
148+
std::optional<std::pair<unsigned, unsigned>> static parseRangeAttribute(
149+
StringRef Attr, bool OnlyFirstRequired = false) {
150+
std::pair<unsigned, unsigned> Val;
151+
std::pair<StringRef, StringRef> Strs = Attr.split(',');
152+
if (Strs.first.trim().getAsInteger(0, Val.first))
153+
return std::nullopt;
154+
if (Strs.second.trim().getAsInteger(0, Val.second)) {
155+
if (!OnlyFirstRequired || !Strs.second.trim().empty())
156+
return std::nullopt;
157+
}
158+
return Val;
159+
}
160+
147161
class AMDGPUInformationCache : public InformationCache {
148162
public:
149163
AMDGPUInformationCache(const Module &M, AnalysisGetter &AG,
@@ -168,9 +182,18 @@ class AMDGPUInformationCache : public InformationCache {
168182
return ST.supportsGetDoorbellID();
169183
}
170184

171-
std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) {
185+
std::optional<std::pair<unsigned, unsigned>>
186+
getFlatWorkGroupSizeAttr(const Function &F) const {
187+
Attribute Attr = F.getFnAttribute("amdgpu-flat-work-group-size");
188+
if (!Attr.isStringAttribute())
189+
return std::nullopt;
190+
return parseRangeAttribute(Attr.getValueAsString());
191+
}
192+
193+
std::pair<unsigned, unsigned>
194+
getDefaultFlatWorkGroupSize(const Function &F) const {
172195
const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
173-
return ST.getFlatWorkGroupSizes(F);
196+
return ST.getDefaultFlatWorkGroupSize(F.getCallingConv());
174197
}
175198

176199
std::pair<unsigned, unsigned>
@@ -733,6 +756,35 @@ struct AAAMDSizeRangeAttribute
733756
return Change;
734757
}
735758

759+
/// Clamp the assumed range to the default value ([Min, Max]) and emit the
760+
/// attribute if it is not same as default.
761+
ChangeStatus
762+
emitAttributeIfNotDefaultAfterClamp(Attributor &A,
763+
std::pair<unsigned, unsigned> Default) {
764+
auto [Min, Max] = Default;
765+
unsigned Lower = getAssumed().getLower().getZExtValue();
766+
unsigned Upper = getAssumed().getUpper().getZExtValue();
767+
768+
// Clamp the range to the default value.
769+
if (Lower < Min)
770+
Lower = Min;
771+
if (Upper > Max + 1)
772+
Upper = Max + 1;
773+
774+
// No manifest if the value is invalid or same as default after clamp.
775+
if ((Lower == Min && Upper == Max + 1) || (Upper < Lower))
776+
return ChangeStatus::UNCHANGED;
777+
778+
Function *F = getAssociatedFunction();
779+
LLVMContext &Ctx = F->getContext();
780+
SmallString<10> Buffer;
781+
raw_svector_ostream OS(Buffer);
782+
OS << Lower << ',' << Upper - 1;
783+
return A.manifestAttrs(getIRPosition(),
784+
{Attribute::get(Ctx, AttrName, OS.str())},
785+
/*ForceReplace=*/true);
786+
}
787+
736788
ChangeStatus emitAttributeIfNotDefault(Attributor &A, unsigned Min,
737789
unsigned Max) {
738790
// Don't add the attribute if it's the implied default.
@@ -767,13 +819,21 @@ struct AAAMDFlatWorkGroupSize : public AAAMDSizeRangeAttribute {
767819
void initialize(Attributor &A) override {
768820
Function *F = getAssociatedFunction();
769821
auto &InfoCache = static_cast<AMDGPUInformationCache &>(A.getInfoCache());
770-
unsigned MinGroupSize, MaxGroupSize;
771-
std::tie(MinGroupSize, MaxGroupSize) = InfoCache.getFlatWorkGroupSizes(*F);
772-
intersectKnown(
773-
ConstantRange(APInt(32, MinGroupSize), APInt(32, MaxGroupSize + 1)));
774822

775-
if (AMDGPU::isEntryFunctionCC(F->getCallingConv()))
776-
indicatePessimisticFixpoint();
823+
bool HasAttr = false;
824+
auto [Min, Max] = InfoCache.getDefaultFlatWorkGroupSize(*F);
825+
826+
if (auto Attr = InfoCache.getFlatWorkGroupSizeAttr(*F)) {
827+
std::tie(Min, Max) = *Attr;
828+
HasAttr = true;
829+
}
830+
831+
ConstantRange Range(APInt(32, Min), APInt(32, Max + 1));
832+
IntegerRangeState RangeState(Range);
833+
clampStateAndIndicateChange(this->getState(), RangeState);
834+
835+
if (HasAttr || AMDGPU::isEntryFunctionCC(F->getCallingConv()))
836+
indicateOptimisticFixpoint();
777837
}
778838

779839
ChangeStatus updateImpl(Attributor &A) override {
@@ -787,9 +847,8 @@ struct AAAMDFlatWorkGroupSize : public AAAMDSizeRangeAttribute {
787847
ChangeStatus manifest(Attributor &A) override {
788848
Function *F = getAssociatedFunction();
789849
auto &InfoCache = static_cast<AMDGPUInformationCache &>(A.getInfoCache());
790-
unsigned Min, Max;
791-
std::tie(Min, Max) = InfoCache.getMaximumFlatWorkGroupRange(*F);
792-
return emitAttributeIfNotDefault(A, Min, Max);
850+
return emitAttributeIfNotDefaultAfterClamp(
851+
A, InfoCache.getMaximumFlatWorkGroupRange(*F));
793852
}
794853

795854
/// See AbstractAttribute::getName()

llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -217,7 +217,7 @@ define ptr addrspace(3) @ret_constant_cast_group_gv_gep_to_flat_to_group() #1 {
217217
; AKF_HSA-NEXT: ret ptr addrspace(3) addrspacecast (ptr addrspace(4) getelementptr ([256 x i32], ptr addrspace(4) addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4)), i64 0, i64 8) to ptr addrspace(3))
218218
;
219219
; ATTRIBUTOR_HSA-LABEL: define {{[^@]+}}@ret_constant_cast_group_gv_gep_to_flat_to_group
220-
; ATTRIBUTOR_HSA-SAME: () #[[ATTR3:[0-9]+]] {
220+
; ATTRIBUTOR_HSA-SAME: () #[[ATTR2]] {
221221
; ATTRIBUTOR_HSA-NEXT: ret ptr addrspace(3) addrspacecast (ptr addrspace(4) getelementptr ([256 x i32], ptr addrspace(4) addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4)), i64 0, i64 8) to ptr addrspace(3))
222222
;
223223
ret ptr addrspace(3) addrspacecast (ptr addrspace(4) getelementptr ([256 x i32], ptr addrspace(4) addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4)), i64 0, i64 8) to ptr addrspace(3))
@@ -235,7 +235,6 @@ attributes #1 = { nounwind }
235235
; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
236236
; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
237237
; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
238-
; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
239238
;.
240239
; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
241240
;.

llvm/test/CodeGen/AMDGPU/amdgpu-attributor-no-agpr.ll

Lines changed: 16 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,7 @@ define amdgpu_kernel void @kernel_uses_asm_physreg_tuple() {
7373

7474
define void @func_uses_asm_virtreg_agpr() {
7575
; CHECK-LABEL: define void @func_uses_asm_virtreg_agpr(
76-
; CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
76+
; CHECK-SAME: ) #[[ATTR0]] {
7777
; CHECK-NEXT: call void asm sideeffect "
7878
; CHECK-NEXT: ret void
7979
;
@@ -83,7 +83,7 @@ define void @func_uses_asm_virtreg_agpr() {
8383

8484
define void @func_uses_asm_physreg_agpr() {
8585
; CHECK-LABEL: define void @func_uses_asm_physreg_agpr(
86-
; CHECK-SAME: ) #[[ATTR2]] {
86+
; CHECK-SAME: ) #[[ATTR0]] {
8787
; CHECK-NEXT: call void asm sideeffect "
8888
; CHECK-NEXT: ret void
8989
;
@@ -93,7 +93,7 @@ define void @func_uses_asm_physreg_agpr() {
9393

9494
define void @func_uses_asm_physreg_agpr_tuple() {
9595
; CHECK-LABEL: define void @func_uses_asm_physreg_agpr_tuple(
96-
; CHECK-SAME: ) #[[ATTR2]] {
96+
; CHECK-SAME: ) #[[ATTR0]] {
9797
; CHECK-NEXT: call void asm sideeffect "
9898
; CHECK-NEXT: ret void
9999
;
@@ -105,7 +105,7 @@ declare void @unknown()
105105

106106
define amdgpu_kernel void @kernel_calls_extern() {
107107
; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern(
108-
; CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
108+
; CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
109109
; CHECK-NEXT: call void @unknown()
110110
; CHECK-NEXT: ret void
111111
;
@@ -115,8 +115,8 @@ define amdgpu_kernel void @kernel_calls_extern() {
115115

116116
define amdgpu_kernel void @kernel_calls_extern_marked_callsite() {
117117
; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_extern_marked_callsite(
118-
; CHECK-SAME: ) #[[ATTR4]] {
119-
; CHECK-NEXT: call void @unknown() #[[ATTR9:[0-9]+]]
118+
; CHECK-SAME: ) #[[ATTR2]] {
119+
; CHECK-NEXT: call void @unknown() #[[ATTR6:[0-9]+]]
120120
; CHECK-NEXT: ret void
121121
;
122122
call void @unknown() #0
@@ -125,7 +125,7 @@ define amdgpu_kernel void @kernel_calls_extern_marked_callsite() {
125125

126126
define amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) {
127127
; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect(
128-
; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR4]] {
128+
; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR2]] {
129129
; CHECK-NEXT: call void [[INDIRECT]]()
130130
; CHECK-NEXT: ret void
131131
;
@@ -135,8 +135,8 @@ define amdgpu_kernel void @kernel_calls_indirect(ptr %indirect) {
135135

136136
define amdgpu_kernel void @kernel_calls_indirect_marked_callsite(ptr %indirect) {
137137
; CHECK-LABEL: define amdgpu_kernel void @kernel_calls_indirect_marked_callsite(
138-
; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR4]] {
139-
; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR9]]
138+
; CHECK-SAME: ptr [[INDIRECT:%.*]]) #[[ATTR2]] {
139+
; CHECK-NEXT: call void [[INDIRECT]]() #[[ATTR6]]
140140
; CHECK-NEXT: ret void
141141
;
142142
call void %indirect() #0
@@ -155,15 +155,15 @@ define amdgpu_kernel void @kernel_transitively_uses_agpr_asm() {
155155

156156
define void @empty() {
157157
; CHECK-LABEL: define void @empty(
158-
; CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
158+
; CHECK-SAME: ) #[[ATTR1]] {
159159
; CHECK-NEXT: ret void
160160
;
161161
ret void
162162
}
163163

164164
define void @also_empty() {
165165
; CHECK-LABEL: define void @also_empty(
166-
; CHECK-SAME: ) #[[ATTR5]] {
166+
; CHECK-SAME: ) #[[ATTR1]] {
167167
; CHECK-NEXT: ret void
168168
;
169169
ret void
@@ -256,12 +256,9 @@ attributes #0 = { "amdgpu-no-agpr" }
256256
;.
257257
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
258258
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
259-
; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
260-
; CHECK: attributes #[[ATTR3:[0-9]+]] = { "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
261-
; CHECK: attributes #[[ATTR4]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
262-
; CHECK: attributes #[[ATTR5]] = { "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,8" "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
263-
; CHECK: attributes #[[ATTR6:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" }
264-
; CHECK: attributes #[[ATTR7:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" }
265-
; CHECK: attributes #[[ATTR8:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" }
266-
; CHECK: attributes #[[ATTR9]] = { "amdgpu-no-agpr" }
259+
; CHECK: attributes #[[ATTR2]] = { "target-cpu"="gfx90a" "uniform-work-group-size"="false" }
260+
; CHECK: attributes #[[ATTR3:[0-9]+]] = { convergent nocallback nofree nosync nounwind willreturn memory(none) "target-cpu"="gfx90a" }
261+
; CHECK: attributes #[[ATTR4:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="gfx90a" }
262+
; CHECK: attributes #[[ATTR5:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) "target-cpu"="gfx90a" }
263+
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-agpr" }
267264
;.

llvm/test/CodeGen/AMDGPU/annotate-existing-abi-attributes.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -117,14 +117,14 @@ define void @call_no_dispatch_id() {
117117
ret void
118118
}
119119
;.
120-
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-workitem-id-x" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
121-
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-workitem-id-y" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
122-
; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
123-
; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-workgroup-id-x" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
124-
; CHECK: attributes #[[ATTR4]] = { "amdgpu-no-workgroup-id-y" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
125-
; CHECK: attributes #[[ATTR5]] = { "amdgpu-no-workgroup-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
126-
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-dispatch-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
127-
; CHECK: attributes #[[ATTR7]] = { "amdgpu-no-queue-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
128-
; CHECK: attributes #[[ATTR8]] = { "amdgpu-no-implicitarg-ptr" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
129-
; CHECK: attributes #[[ATTR9]] = { "amdgpu-no-dispatch-id" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
120+
; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-workitem-id-x" "uniform-work-group-size"="false" }
121+
; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-workitem-id-y" "uniform-work-group-size"="false" }
122+
; CHECK: attributes #[[ATTR2]] = { "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
123+
; CHECK: attributes #[[ATTR3]] = { "amdgpu-no-workgroup-id-x" "uniform-work-group-size"="false" }
124+
; CHECK: attributes #[[ATTR4]] = { "amdgpu-no-workgroup-id-y" "uniform-work-group-size"="false" }
125+
; CHECK: attributes #[[ATTR5]] = { "amdgpu-no-workgroup-id-z" "uniform-work-group-size"="false" }
126+
; CHECK: attributes #[[ATTR6]] = { "amdgpu-no-dispatch-ptr" "uniform-work-group-size"="false" }
127+
; CHECK: attributes #[[ATTR7]] = { "amdgpu-no-queue-ptr" "uniform-work-group-size"="false" }
128+
; CHECK: attributes #[[ATTR8]] = { "amdgpu-no-implicitarg-ptr" "uniform-work-group-size"="false" }
129+
; CHECK: attributes #[[ATTR9]] = { "amdgpu-no-dispatch-id" "uniform-work-group-size"="false" }
130130
;.

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