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[AArch64][SME2] Add multi-vector frint intrinsics
Adds x2 and x4 vector intrinsics for the following instructions: - frinta - frintm - frintn - frintp NOTE: These intrinsics are still in development and are subject to future changes. Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D143058
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‎llvm/include/llvm/IR/IntrinsicsAArch64.td

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Original file line numberDiff line numberDiff line change
@@ -3044,6 +3044,13 @@ let TargetPrefix = "aarch64" in {
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def int_aarch64_sve_sqdmulh_vgx2 : SME2_VG2_Multi_Multi_Intrinsic;
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def int_aarch64_sve_sqdmulh_vgx4 : SME2_VG4_Multi_Multi_Intrinsic;
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// Multi-vector floating-point round to integral value
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foreach inst = ["a", "m", "n", "p"] in {
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def int_aarch64_sve_frint # inst # _x2 : SVE2_VG2_ZipUzp_Intrinsic;
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def int_aarch64_sve_frint # inst # _x4 : SVE2_VG4_ZipUzp_Intrinsic;
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}
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//
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// Multi-vector min/max
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//

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

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Original file line numberDiff line numberDiff line change
@@ -367,6 +367,7 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
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void SelectClamp(SDNode *N, unsigned NumVecs, unsigned Opcode);
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void SelectUnaryMultiIntrinsic(SDNode *N, unsigned NumOutVecs,
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bool IsTupleInput, unsigned Opc);
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void SelectFrintFromVT(SDNode *N, unsigned NumVecs, unsigned Opcode);
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template <unsigned MaxIdx, unsigned Scale>
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void SelectMultiVectorMove(SDNode *N, unsigned NumVecs, unsigned BaseReg,
@@ -1874,6 +1875,13 @@ void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs,
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CurDAG->RemoveDeadNode(N);
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}
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void AArch64DAGToDAGISel::SelectFrintFromVT(SDNode *N, unsigned NumVecs,
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unsigned Opcode) {
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if (N->getValueType(0) != MVT::nxv4f32)
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return;
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SelectUnaryMultiIntrinsic(N, NumVecs, true, Opcode);
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}
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void AArch64DAGToDAGISel::SelectClamp(SDNode *N, unsigned NumVecs,
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unsigned Op) {
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SDLoc DL(N);
@@ -5380,6 +5388,30 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
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SelectUnaryMultiIntrinsic(Node, 4, /*IsTupleInput=*/true,
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AArch64::UZP_VG4_4Z4Z_Q);
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return;
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case Intrinsic::aarch64_sve_frinta_x2:
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SelectFrintFromVT(Node, 2, AArch64::FRINTA_2Z2Z_S);
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return;
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case Intrinsic::aarch64_sve_frinta_x4:
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SelectFrintFromVT(Node, 4, AArch64::FRINTA_4Z4Z_S);
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return;
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case Intrinsic::aarch64_sve_frintm_x2:
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SelectFrintFromVT(Node, 2, AArch64::FRINTM_2Z2Z_S);
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return;
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case Intrinsic::aarch64_sve_frintm_x4:
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SelectFrintFromVT(Node, 4, AArch64::FRINTM_4Z4Z_S);
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return;
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case Intrinsic::aarch64_sve_frintn_x2:
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SelectFrintFromVT(Node, 2, AArch64::FRINTN_2Z2Z_S);
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return;
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case Intrinsic::aarch64_sve_frintn_x4:
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SelectFrintFromVT(Node, 4, AArch64::FRINTN_4Z4Z_S);
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return;
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case Intrinsic::aarch64_sve_frintp_x2:
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SelectFrintFromVT(Node, 2, AArch64::FRINTP_2Z2Z_S);
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return;
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case Intrinsic::aarch64_sve_frintp_x4:
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SelectFrintFromVT(Node, 4, AArch64::FRINTP_4Z4Z_S);
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return;
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}
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break;
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}

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-frint.ll

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -verify-machineinstrs < %s | FileCheck %s
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; FRINTA
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define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_frinta_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2) {
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; CHECK-LABEL: multi_vec_frinta_x2_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z3.d, z2.d
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; CHECK-NEXT: mov z2.d, z1.d
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; CHECK-NEXT: frinta { z0.s, z1.s }, { z2.s, z3.s }
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2)
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ret { <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_frinta_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4) {
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; CHECK-LABEL: multi_vec_frinta_x4_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: frinta { z0.s - z3.s }, { z4.s - z7.s }
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4)
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ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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; FRINTM
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define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_frintm_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2) {
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; CHECK-LABEL: multi_vec_frintm_x2_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z3.d, z2.d
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; CHECK-NEXT: mov z2.d, z1.d
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; CHECK-NEXT: frintm { z0.s, z1.s }, { z2.s, z3.s }
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2)
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ret { <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_frintm_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4) {
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; CHECK-LABEL: multi_vec_frintm_x4_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: frintm { z0.s - z3.s }, { z4.s - z7.s }
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4)
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ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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; FRINTN
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define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_frintn_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2) {
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; CHECK-LABEL: multi_vec_frintn_x2_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z3.d, z2.d
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; CHECK-NEXT: mov z2.d, z1.d
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; CHECK-NEXT: frintn { z0.s, z1.s }, { z2.s, z3.s }
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x2.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2)
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ret { <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_frintn_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4) {
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; CHECK-LABEL: multi_vec_frintn_x4_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: frintn { z0.s - z3.s }, { z4.s - z7.s }
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x4.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4)
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ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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; FRINTP
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define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_frintp_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2) {
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; CHECK-LABEL: multi_vec_frintp_x2_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z3.d, z2.d
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; CHECK-NEXT: mov z2.d, z1.d
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; CHECK-NEXT: frintp { z0.s, z1.s }, { z2.s, z3.s }
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintp.x2.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2)
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ret { <vscale x 4 x float>, <vscale x 4 x float> } %res
93+
}
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define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_frintp_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4) {
96+
; CHECK-LABEL: multi_vec_frintp_x4_f32:
97+
; CHECK: // %bb.0:
98+
; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
102+
; CHECK-NEXT: frintp { z0.s - z3.s }, { z4.s - z7.s }
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; CHECK-NEXT: ret
104+
%res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintp.x4.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3, <vscale x 4 x float> %zn4)
105+
ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
106+
}
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108+
declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
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declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frinta.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
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declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
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declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintm.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
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declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
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declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintn.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)
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declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintp.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
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declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.frintp.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)

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