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[AArch64] Generate zeroing forms of certain SVE2.2 instructions (7/11)
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4277,7 +4277,7 @@ let Predicates = [HasSVE2p2orSME2p2] in {
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defm SCVTF_ZPzZ : sve_fp_z2op_p_zd_c<0b0, "scvtf", "int_aarch64_sve_scvtf", AArch64scvtf_mt>;
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defm UCVTF_ZPzZ : sve_fp_z2op_p_zd_c<0b1, "ucvtf", "int_aarch64_sve_ucvtf", AArch64ucvtf_mt>;
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// Signed integer base 2 logarithm of fp value, zeroing predicate
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defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb">;
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defm FLOGB_ZPzZ : sve_fp_z2op_p_zd_d_flogb<"flogb", int_aarch64_sve_flogb>;
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// SVE2 integer unary operations, zeroing predicate
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def URECPE_ZPzZ : sve2_int_un_pred_arit_z<0b10, 0b00, "urecpe", ZPR32>;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3331,10 +3331,14 @@ multiclass sve_fp_z2op_p_zd_c<bit U, string asm, string int_op, SDPatternOperato
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def : SVE_1_Op_PassthruUndefZero_Pat<nxv2f64, ir_op, nxv2i1,nxv2i64, !cast<Instruction>(NAME # _DtoD)>;
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}
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3334-
multiclass sve_fp_z2op_p_zd_d_flogb<string asm> {
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multiclass sve_fp_z2op_p_zd_d_flogb<string asm, SDPatternOperator op> {
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def _H : sve_fp_z2op_p_zd<0b0011001, asm, ZPR16, ZPR16>;
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def _S : sve_fp_z2op_p_zd<0b0011010, asm, ZPR32, ZPR32>;
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def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>;
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def : SVE_3_Op_UndefZero_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
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def : SVE_3_Op_UndefZero_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_UndefZero_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve_fp_z2op_p_zd_b_0<string asm, string op> {

‎llvm/test/CodeGen/AArch64/zeroing-forms-flogb.ll

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,146 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mattr=+sve2 < %s | FileCheck %s
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; RUN: llc -mattr=+sve2p2 < %s | FileCheck %s -check-prefix CHECK-2p2
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; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s
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; RUN: llc -mattr=+sme2p2 -force-streaming < %s | FileCheck %s -check-prefix CHECK-2p2
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target triple = "aarch64-linux"
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define <vscale x 8 x i16> @test_svlogb_f16_x_1(<vscale x 8 x i1> %pg, <vscale x 8 x half> %x) {
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; CHECK-LABEL: test_svlogb_f16_x_1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: flogb z0.h, p0/m, z0.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f16_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.h, p0/z, z0.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
22+
ret <vscale x 8 x i16> %0
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}
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define <vscale x 8 x i16> @test_svlogb_f16_x_2(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
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; CHECK-LABEL: test_svlogb_f16_x_2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: flogb z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f16_x_2:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.h, p0/z, z1.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
37+
ret <vscale x 8 x i16> %0
38+
}
39+
40+
define <vscale x 8 x i16> @test_svlogb_f16_z(<vscale x 8 x i1> %pg, double %z0, <vscale x 8 x half> %x) {
41+
; CHECK-LABEL: test_svlogb_f16_z:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.h, #0 // =0x0
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; CHECK-NEXT: flogb z0.h, p0/m, z1.h
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f16_z:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.h, p0/z, z1.h
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
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ret <vscale x 8 x i16> %0
54+
}
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define <vscale x 4 x i32> @test_svlogb_f32_x_1(<vscale x 4 x i1> %pg, <vscale x 4 x float> %x) {
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; CHECK-LABEL: test_svlogb_f32_x_1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: flogb z0.s, p0/m, z0.s
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f32_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.s, p0/z, z0.s
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
68+
ret <vscale x 4 x i32> %0
69+
}
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define <vscale x 4 x i32> @test_svlogb_f32_x_2(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
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; CHECK-LABEL: test_svlogb_f32_x_2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: flogb z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f32_x_2:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.s, p0/z, z1.s
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; CHECK-2p2-NEXT: ret
81+
entry:
82+
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
83+
ret <vscale x 4 x i32> %0
84+
}
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86+
define <vscale x 4 x i32> @test_svlogb_f32_z(<vscale x 4 x i1> %pg, double %z0, <vscale x 4 x float> %x) {
87+
; CHECK-LABEL: test_svlogb_f32_z:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.s, #0 // =0x0
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; CHECK-NEXT: flogb z0.s, p0/m, z1.s
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f32_z:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.s, p0/z, z1.s
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; CHECK-2p2-NEXT: ret
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entry:
98+
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
99+
ret <vscale x 4 x i32> %0
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}
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define <vscale x 2 x i64> @test_svlogb_f64_x_1(<vscale x 2 x i1> %pg, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_svlogb_f64_x_1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: flogb z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f64_x_1:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.d, p0/z, z0.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 2 x i64> @test_svlogb_f64_x_2(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_svlogb_f64_x_2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: flogb z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f64_x_2:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.d, p0/z, z1.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
129+
ret <vscale x 2 x i64> %0
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}
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define <vscale x 2 x i64> @test_svlogb_f64_z(<vscale x 2 x i1> %pg, double %z0, <vscale x 2 x double> %x) {
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; CHECK-LABEL: test_svlogb_f64_z:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.d, #0 // =0x0
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; CHECK-NEXT: flogb z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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;
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; CHECK-2p2-LABEL: test_svlogb_f64_z:
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; CHECK-2p2: // %bb.0: // %entry
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; CHECK-2p2-NEXT: flogb z0.d, p0/z, z1.d
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; CHECK-2p2-NEXT: ret
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entry:
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%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
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ret <vscale x 2 x i64> %0
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}

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