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[RISCV] Use BuildPairF64 and SplitF64 for bitcast i64<->f64 on rv32 regardless of Zfa. (#85982)
Previously we used BuildPairF64 and SplitF64 only if Zfa was supported since they will select register file moves that are only available with Zfa. We recently changed the handling of BuildPairF64/SplitF64 for Zdinx to not go through memory so we should use that for bitcast. That leaves the D without Zfa case that does need to go through memory. Previously we let type legalization expand to loads and stores using a new stack temporary created for each bitcast. After this patch we will create the loads ands stores in the custom inserter and share the same stack slot for all. This also allows DAGCombiner to optimize when bitcast is mixed with BuildPairF64/SplitF64.
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5 files changed

+21
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -559,11 +559,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
559559
if (Subtarget.hasStdExtDOrZdinx()) {
560560
setOperationAction(FPLegalNodeTypes, MVT::f64, Legal);
561561

562+
if (!Subtarget.is64Bit())
563+
setOperationAction(ISD::BITCAST, MVT::i64, Custom);
564+
562565
if (Subtarget.hasStdExtZfa()) {
563566
setOperationAction(FPRndMode, MVT::f64, Legal);
564567
setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
565-
if (!Subtarget.is64Bit())
566-
setOperationAction(ISD::BITCAST, MVT::i64, Custom);
567568
} else {
568569
if (Subtarget.is64Bit())
569570
setOperationAction(FPRndMode, MVT::f64, Custom);
@@ -6071,8 +6072,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
60716072
DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
60726073
return FPConv;
60736074
}
6074-
if (VT == MVT::f64 && Op0VT == MVT::i64 && XLenVT == MVT::i32 &&
6075-
Subtarget.hasStdExtZfa()) {
6075+
if (VT == MVT::f64 && Op0VT == MVT::i64 && XLenVT == MVT::i32) {
60766076
SDValue Lo, Hi;
60776077
std::tie(Lo, Hi) = DAG.SplitScalar(Op0, DL, MVT::i32, MVT::i32);
60786078
SDValue RetReg =
@@ -12157,8 +12157,7 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
1215712157
SDValue FPConv =
1215812158
DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
1215912159
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
12160-
} else if (VT == MVT::i64 && Op0VT == MVT::f64 && XLenVT == MVT::i32 &&
12161-
Subtarget.hasStdExtZfa()) {
12160+
} else if (VT == MVT::i64 && Op0VT == MVT::f64 && XLenVT == MVT::i32) {
1216212161
SDValue NewReg = DAG.getNode(RISCVISD::SplitF64, DL,
1216312162
DAG.getVTList(MVT::i32, MVT::i32), Op0);
1216412163
SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,

‎llvm/test/CodeGen/RISCV/double-convert.ll

Lines changed: 6 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1116,13 +1116,7 @@ define i64 @fmv_x_d(double %a, double %b) nounwind {
11161116
;
11171117
; RV32IZFINXZDINX-LABEL: fmv_x_d:
11181118
; RV32IZFINXZDINX: # %bb.0:
1119-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
11201119
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
1121-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1122-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1123-
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
1124-
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
1125-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
11261120
; RV32IZFINXZDINX-NEXT: ret
11271121
;
11281122
; RV64IZFINXZDINX-LABEL: fmv_x_d:
@@ -1257,13 +1251,13 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
12571251
; RV32IFD-LABEL: fmv_d_x:
12581252
; RV32IFD: # %bb.0:
12591253
; RV32IFD-NEXT: addi sp, sp, -16
1260-
; RV32IFD-NEXT: sw a3, 4(sp)
1261-
; RV32IFD-NEXT: sw a2, 0(sp)
1262-
; RV32IFD-NEXT: sw a1, 12(sp)
12631254
; RV32IFD-NEXT: sw a0, 8(sp)
1264-
; RV32IFD-NEXT: fld fa5, 0(sp)
1255+
; RV32IFD-NEXT: sw a1, 12(sp)
1256+
; RV32IFD-NEXT: fld fa5, 8(sp)
1257+
; RV32IFD-NEXT: sw a2, 8(sp)
1258+
; RV32IFD-NEXT: sw a3, 12(sp)
12651259
; RV32IFD-NEXT: fld fa4, 8(sp)
1266-
; RV32IFD-NEXT: fadd.d fa0, fa4, fa5
1260+
; RV32IFD-NEXT: fadd.d fa0, fa5, fa4
12671261
; RV32IFD-NEXT: addi sp, sp, 16
12681262
; RV32IFD-NEXT: ret
12691263
;
@@ -1276,17 +1270,7 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
12761270
;
12771271
; RV32IZFINXZDINX-LABEL: fmv_d_x:
12781272
; RV32IZFINXZDINX: # %bb.0:
1279-
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1280-
; RV32IZFINXZDINX-NEXT: sw a3, 4(sp)
1281-
; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
1282-
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
1283-
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
1284-
; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
1285-
; RV32IZFINXZDINX-NEXT: lw a1, 4(sp)
1286-
; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
1287-
; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
1288-
; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
1289-
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1273+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
12901274
; RV32IZFINXZDINX-NEXT: ret
12911275
;
12921276
; RV64IZFINXZDINX-LABEL: fmv_d_x:

‎llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll

Lines changed: 1 addition & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -75,24 +75,10 @@ define double @constraint_f_double_abi_name(double %a) nounwind {
7575
define double @constraint_gpr(double %x) {
7676
; RV32F-LABEL: constraint_gpr:
7777
; RV32F: # %bb.0:
78-
; RV32F-NEXT: addi sp, sp, -32
79-
; RV32F-NEXT: .cfi_def_cfa_offset 32
80-
; RV32F-NEXT: sw a0, 8(sp)
81-
; RV32F-NEXT: sw a1, 12(sp)
82-
; RV32F-NEXT: fld fa5, 8(sp)
83-
; RV32F-NEXT: fsd fa5, 24(sp)
84-
; RV32F-NEXT: lw a0, 24(sp)
85-
; RV32F-NEXT: lw a1, 28(sp)
78+
; RV32F-NEXT: .cfi_def_cfa_offset 0
8679
; RV32F-NEXT: #APP
8780
; RV32F-NEXT: mv a0, a0
8881
; RV32F-NEXT: #NO_APP
89-
; RV32F-NEXT: sw a1, 20(sp)
90-
; RV32F-NEXT: sw a0, 16(sp)
91-
; RV32F-NEXT: fld fa5, 16(sp)
92-
; RV32F-NEXT: fsd fa5, 8(sp)
93-
; RV32F-NEXT: lw a0, 8(sp)
94-
; RV32F-NEXT: lw a1, 12(sp)
95-
; RV32F-NEXT: addi sp, sp, 32
9682
; RV32F-NEXT: ret
9783
;
9884
; RV64F-LABEL: constraint_gpr:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -416,8 +416,8 @@ define double @bitcast_v1i64_f64(<1 x i64> %a) {
416416
; RV32ELEN32: # %bb.0:
417417
; RV32ELEN32-NEXT: addi sp, sp, -16
418418
; RV32ELEN32-NEXT: .cfi_def_cfa_offset 16
419-
; RV32ELEN32-NEXT: sw a1, 12(sp)
420419
; RV32ELEN32-NEXT: sw a0, 8(sp)
420+
; RV32ELEN32-NEXT: sw a1, 12(sp)
421421
; RV32ELEN32-NEXT: fld fa0, 8(sp)
422422
; RV32ELEN32-NEXT: addi sp, sp, 16
423423
; RV32ELEN32-NEXT: ret

‎llvm/test/CodeGen/RISCV/spill-fill-fold.ll

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -290,8 +290,8 @@ define double @spill_i64_to_double(i64 %a) nounwind {
290290
; RV32ID-NEXT: fsd fs9, 40(sp) # 8-byte Folded Spill
291291
; RV32ID-NEXT: fsd fs10, 32(sp) # 8-byte Folded Spill
292292
; RV32ID-NEXT: fsd fs11, 24(sp) # 8-byte Folded Spill
293-
; RV32ID-NEXT: sw a1, 20(sp)
294293
; RV32ID-NEXT: sw a0, 16(sp)
294+
; RV32ID-NEXT: sw a1, 20(sp)
295295
; RV32ID-NEXT: fld fa5, 16(sp)
296296
; RV32ID-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
297297
; RV32ID-NEXT: #APP
@@ -804,13 +804,15 @@ define double @fill_i64_to_double(i64 %a) nounwind {
804804
; RV32ID-NEXT: fsd fs9, 40(sp) # 8-byte Folded Spill
805805
; RV32ID-NEXT: fsd fs10, 32(sp) # 8-byte Folded Spill
806806
; RV32ID-NEXT: fsd fs11, 24(sp) # 8-byte Folded Spill
807-
; RV32ID-NEXT: sw a1, 20(sp)
808-
; RV32ID-NEXT: sw a0, 16(sp)
809-
; RV32ID-NEXT: fld fa5, 16(sp)
810-
; RV32ID-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
807+
; RV32ID-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
808+
; RV32ID-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
811809
; RV32ID-NEXT: #APP
812810
; RV32ID-NEXT: #NO_APP
813-
; RV32ID-NEXT: fld fa0, 8(sp) # 8-byte Folded Reload
811+
; RV32ID-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
812+
; RV32ID-NEXT: sw a0, 16(sp)
813+
; RV32ID-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
814+
; RV32ID-NEXT: sw a0, 20(sp)
815+
; RV32ID-NEXT: fld fa0, 16(sp)
814816
; RV32ID-NEXT: lw ra, 172(sp) # 4-byte Folded Reload
815817
; RV32ID-NEXT: lw s0, 168(sp) # 4-byte Folded Reload
816818
; RV32ID-NEXT: lw s1, 164(sp) # 4-byte Folded Reload

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