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[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163)
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5 files changed

+42
-32
lines changed

5 files changed

+42
-32
lines changed

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,9 @@ enum OperandType : unsigned {
335335
OPERAND_FRMARG,
336336
// Operand is a 3-bit rounding mode where only RTZ is valid.
337337
OPERAND_RTZARG,
338-
OPERAND_LAST_RISCV_IMM = OPERAND_RTZARG,
338+
// Condition code used by select and short forward branch pseudos.
339+
OPERAND_COND_CODE,
340+
OPERAND_LAST_RISCV_IMM = OPERAND_COND_CODE,
339341
// Operand is either a register or uimm5, this is used by V extension pseudo
340342
// instructions to represent a value that be passed as AVL to either vsetvli
341343
// or vsetivli.

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2542,6 +2542,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
25422542
case RISCVOp::OPERAND_RTZARG:
25432543
Ok = Imm == RISCVFPRndMode::RTZ;
25442544
break;
2545+
case RISCVOp::OPERAND_COND_CODE:
2546+
Ok = Imm >= 0 && Imm < RISCVCC::COND_INVALID;
2547+
break;
25452548
}
25462549
if (!Ok) {
25472550
ErrInfo = "Invalid immediate";

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -387,6 +387,11 @@ def csr_sysreg : RISCVOp, TImmLeaf<XLenVT, "return isUInt<12>(Imm);"> {
387387
// A parameterized register class alternative to i32imm/i64imm from Target.td.
388388
def ixlenimm : Operand<XLenVT>;
389389

390+
// Condition code used by select and short forward branch pseudos.
391+
def cond_code : RISCVOp {
392+
let OperandType = "OPERAND_COND_CODE";
393+
}
394+
390395
def ixlenimm_li : Operand<XLenVT> {
391396
let ParserMatchClass = ImmXLenAsmOperand<"", "LI">;
392397
}
@@ -1450,7 +1455,7 @@ def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,
14501455
multiclass SelectCC_GPR_rrirr<DAGOperand valty, ValueType vt> {
14511456
let usesCustomInserter = 1 in
14521457
def _Using_CC_GPR : Pseudo<(outs valty:$dst),
1453-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
1458+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
14541459
valty:$truev, valty:$falsev),
14551460
[(set valty:$dst,
14561461
(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), GPR:$rhs, cond,

‎llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ let Predicates = [HasShortForwardBranchOpt], isSelect = 1,
1515
// This instruction moves $truev to $dst when the condition is true. It will
1616
// be expanded to control flow in RISCVExpandPseudoInsts.
1717
def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst),
18-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
18+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
1919
GPR:$falsev, GPR:$truev),
2020
[(set GPR:$dst,
2121
(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
@@ -34,7 +34,7 @@ let Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt],
3434
// be expanded to control flow in RISCVExpandPseudoInsts.
3535
// We use GPRNoX0 because c.mv cannot encode X0.
3636
def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst),
37-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
37+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
3838
GPRNoX0:$falsev, GPRNoX0:$truev),
3939
[(set GPRNoX0:$dst,
4040
(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs),
@@ -51,143 +51,143 @@ def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst),
5151
let Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0,
5252
mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in {
5353
def PseudoCCADD : Pseudo<(outs GPR:$dst),
54-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
54+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
5555
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
5656
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
5757
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
5858
def PseudoCCSUB : Pseudo<(outs GPR:$dst),
59-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
59+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
6060
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
6161
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
6262
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
6363
def PseudoCCSLL : Pseudo<(outs GPR:$dst),
64-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
64+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
6565
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
6666
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
6767
ReadSFBALU, ReadSFBALU]>;
6868
def PseudoCCSRL : Pseudo<(outs GPR:$dst),
69-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
69+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
7070
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
7171
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
7272
ReadSFBALU, ReadSFBALU]>;
7373
def PseudoCCSRA : Pseudo<(outs GPR:$dst),
74-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
74+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
7575
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
7676
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
7777
ReadSFBALU, ReadSFBALU]>;
7878
def PseudoCCAND : Pseudo<(outs GPR:$dst),
79-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
79+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
8080
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
8181
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
8282
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
8383
def PseudoCCOR : Pseudo<(outs GPR:$dst),
84-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
84+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
8585
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
8686
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
8787
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
8888
def PseudoCCXOR : Pseudo<(outs GPR:$dst),
89-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
89+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
9090
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
9191
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
9292
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
9393

9494
def PseudoCCADDI : Pseudo<(outs GPR:$dst),
95-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
95+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
9696
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
9797
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
9898
ReadSFBALU]>;
9999
def PseudoCCSLLI : Pseudo<(outs GPR:$dst),
100-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
100+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
101101
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
102102
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
103103
ReadSFBALU]>;
104104
def PseudoCCSRLI : Pseudo<(outs GPR:$dst),
105-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
105+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
106106
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
107107
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
108108
ReadSFBALU]>;
109109
def PseudoCCSRAI : Pseudo<(outs GPR:$dst),
110-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
110+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
111111
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
112112
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
113113
ReadSFBALU]>;
114114
def PseudoCCANDI : Pseudo<(outs GPR:$dst),
115-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
115+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
116116
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
117117
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
118118
ReadSFBALU]>;
119119
def PseudoCCORI : Pseudo<(outs GPR:$dst),
120-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
120+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
121121
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
122122
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
123123
ReadSFBALU]>;
124124
def PseudoCCXORI : Pseudo<(outs GPR:$dst),
125-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
125+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
126126
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
127127
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
128128
ReadSFBALU]>;
129129

130130
// RV64I instructions
131131
def PseudoCCADDW : Pseudo<(outs GPR:$dst),
132-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
132+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
133133
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
134134
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
135135
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
136136
def PseudoCCSUBW : Pseudo<(outs GPR:$dst),
137-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
137+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
138138
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
139139
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
140140
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
141141
def PseudoCCSLLW : Pseudo<(outs GPR:$dst),
142-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
142+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
143143
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
144144
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
145145
ReadSFBALU, ReadSFBALU]>;
146146
def PseudoCCSRLW : Pseudo<(outs GPR:$dst),
147-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
147+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
148148
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
149149
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
150150
ReadSFBALU, ReadSFBALU]>;
151151
def PseudoCCSRAW : Pseudo<(outs GPR:$dst),
152-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
152+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
153153
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
154154
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
155155
ReadSFBALU, ReadSFBALU]>;
156156

157157
def PseudoCCADDIW : Pseudo<(outs GPR:$dst),
158-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
158+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
159159
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
160160
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
161161
ReadSFBALU]>;
162162
def PseudoCCSLLIW : Pseudo<(outs GPR:$dst),
163-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
163+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
164164
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
165165
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
166166
ReadSFBALU]>;
167167
def PseudoCCSRLIW : Pseudo<(outs GPR:$dst),
168-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
168+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
169169
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
170170
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
171171
ReadSFBALU]>;
172172
def PseudoCCSRAIW : Pseudo<(outs GPR:$dst),
173-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
173+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
174174
GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
175175
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
176176
ReadSFBALU]>;
177177

178178
// Zbb/Zbkb instructions
179179
def PseudoCCANDN : Pseudo<(outs GPR:$dst),
180-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
180+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
181181
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
182182
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
183183
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
184184
def PseudoCCORN : Pseudo<(outs GPR:$dst),
185-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
185+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
186186
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
187187
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
188188
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
189189
def PseudoCCXNOR : Pseudo<(outs GPR:$dst),
190-
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
190+
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc,
191191
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
192192
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
193193
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -818,7 +818,7 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
818818

819819
let usesCustomInserter = 1 in
820820
def Select_GPR_Using_CC_Imm : Pseudo<(outs GPR:$dst),
821-
(ins GPR:$lhs, simm5:$imm5, ixlenimm:$cc,
821+
(ins GPR:$lhs, simm5:$imm5, cond_code:$cc,
822822
GPR:$truev, GPR:$falsev), []>;
823823

824824

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