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[RISCV] Extract tryUnsignedBitfieldExtract as a member function of RISCVDAGToDAGISel. NFC.
1 parent cd84ba2 commit f88fd89

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2 files changed

+20
-21
lines changed

2 files changed

+20
-21
lines changed

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 18 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -663,6 +663,20 @@ bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
663663
return false;
664664
}
665665

666+
bool RISCVDAGToDAGISel::tryUnsignedBitfieldExtract(SDNode *Node, SDLoc DL,
667+
MVT VT, SDValue X,
668+
unsigned Msb, unsigned Lsb) {
669+
// Only supported with XTHeadBb at the moment.
670+
if (!Subtarget->hasVendorXTHeadBb())
671+
return false;
672+
673+
SDNode *TH_EXTU = CurDAG->getMachineNode(
674+
RISCV::TH_EXTU, DL, VT, X, CurDAG->getTargetConstant(Msb, DL, VT),
675+
CurDAG->getTargetConstant(Lsb, DL, VT));
676+
ReplaceNode(Node, TH_EXTU);
677+
return true;
678+
}
679+
666680
bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
667681
// Target does not support indexed loads.
668682
if (!Subtarget->hasVendorXTHeadMemIdx())
@@ -1122,16 +1136,12 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
11221136
return;
11231137
}
11241138

1125-
unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
1126-
if (Subtarget->hasVendorXTHeadBb()) {
1127-
SDNode *THEXTU = CurDAG->getMachineNode(
1128-
RISCV::TH_EXTU, DL, VT, N0->getOperand(0),
1129-
CurDAG->getTargetConstant(TrailingOnes - 1, DL, VT),
1130-
CurDAG->getTargetConstant(ShAmt, DL, VT));
1131-
ReplaceNode(Node, THEXTU);
1139+
const unsigned Msb = TrailingOnes - 1;
1140+
const unsigned Lsb = ShAmt;
1141+
if (tryUnsignedBitfieldExtract(Node, DL, VT, N0->getOperand(0), Msb, Lsb))
11321142
return;
1133-
}
11341143

1144+
unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
11351145
SDNode *SLLI =
11361146
CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
11371147
CurDAG->getTargetConstant(LShAmt, DL, VT));
@@ -1188,19 +1198,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
11881198

11891199
SDValue N0 = Node->getOperand(0);
11901200

1191-
auto tryUnsignedBitfieldExtract = [&](SDNode *Node, SDLoc DL, MVT VT,
1192-
SDValue X, unsigned Msb,
1193-
unsigned Lsb) {
1194-
if (!Subtarget->hasVendorXTHeadBb())
1195-
return false;
1196-
1197-
SDNode *TH_EXTU = CurDAG->getMachineNode(
1198-
RISCV::TH_EXTU, DL, VT, X, CurDAG->getTargetConstant(Msb, DL, VT),
1199-
CurDAG->getTargetConstant(Lsb, DL, VT));
1200-
ReplaceNode(Node, TH_EXTU);
1201-
return true;
1202-
};
1203-
12041201
bool LeftShift = N0.getOpcode() == ISD::SHL;
12051202
if (LeftShift || N0.getOpcode() == ISD::SRL) {
12061203
auto *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,8 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
8181

8282
bool tryShrinkShlLogicImm(SDNode *Node);
8383
bool trySignedBitfieldExtract(SDNode *Node);
84+
bool tryUnsignedBitfieldExtract(SDNode *Node, SDLoc DL, MVT VT, SDValue X,
85+
unsigned Msb, unsigned Lsb);
8486
bool tryIndexedLoad(SDNode *Node);
8587

8688
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);

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