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[RISCV] Add tests for length changing shuffles
Tests taken from Luke's 88147 with minimal changes by me (preames). The main case of interest here is when mask length is less than source length (i.e. length is decreasing). We often scalarize these, which on RISCV can be quite painful.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck -check-prefixes=CHECK,RV32 %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck -check-prefixes=CHECK,RV64 %s
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define <8 x i1> @v8i1_v16i1(<16 x i1>) {
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; RV32-LABEL: v8i1_v16i1:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; RV32-NEXT: vmv.x.s a0, v0
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; RV32-NEXT: slli a1, a0, 19
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; RV32-NEXT: srli a1, a1, 31
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; RV32-NEXT: slli a2, a0, 26
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; RV32-NEXT: srli a2, a2, 31
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; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; RV32-NEXT: vmv.v.x v8, a2
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; RV32-NEXT: vslide1down.vx v8, v8, a1
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; RV32-NEXT: slli a1, a0, 24
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; RV32-NEXT: srli a1, a1, 31
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; RV32-NEXT: vslide1down.vx v8, v8, a1
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; RV32-NEXT: slli a1, a0, 29
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; RV32-NEXT: srli a1, a1, 31
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; RV32-NEXT: vslide1down.vx v8, v8, a1
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; RV32-NEXT: slli a1, a0, 18
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; RV32-NEXT: srli a1, a1, 31
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; RV32-NEXT: slli a2, a0, 16
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; RV32-NEXT: srli a2, a2, 31
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; RV32-NEXT: vmv.v.x v9, a2
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; RV32-NEXT: vslide1down.vx v9, v9, a1
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; RV32-NEXT: slli a1, a0, 27
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; RV32-NEXT: srli a1, a1, 31
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; RV32-NEXT: vslide1down.vx v9, v9, a1
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; RV32-NEXT: slli a0, a0, 28
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; RV32-NEXT: srli a0, a0, 31
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; RV32-NEXT: vmv.v.i v0, 15
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; RV32-NEXT: vslide1down.vx v9, v9, a0
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; RV32-NEXT: vslidedown.vi v9, v8, 4, v0.t
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; RV32-NEXT: vand.vi v8, v9, 1
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; RV32-NEXT: vmsne.vi v0, v8, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v8i1_v16i1:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; RV64-NEXT: vmv.x.s a0, v0
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; RV64-NEXT: slli a1, a0, 51
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; RV64-NEXT: srli a1, a1, 63
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; RV64-NEXT: slli a2, a0, 58
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; RV64-NEXT: srli a2, a2, 63
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; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; RV64-NEXT: vmv.v.x v8, a2
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; RV64-NEXT: vslide1down.vx v8, v8, a1
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; RV64-NEXT: slli a1, a0, 56
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; RV64-NEXT: srli a1, a1, 63
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; RV64-NEXT: vslide1down.vx v8, v8, a1
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; RV64-NEXT: slli a1, a0, 61
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; RV64-NEXT: srli a1, a1, 63
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; RV64-NEXT: vslide1down.vx v8, v8, a1
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; RV64-NEXT: slli a1, a0, 50
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; RV64-NEXT: srli a1, a1, 63
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; RV64-NEXT: slli a2, a0, 48
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; RV64-NEXT: srli a2, a2, 63
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; RV64-NEXT: vmv.v.x v9, a2
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; RV64-NEXT: vslide1down.vx v9, v9, a1
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; RV64-NEXT: slli a1, a0, 59
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; RV64-NEXT: srli a1, a1, 63
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; RV64-NEXT: vslide1down.vx v9, v9, a1
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; RV64-NEXT: slli a0, a0, 60
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; RV64-NEXT: srli a0, a0, 63
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; RV64-NEXT: vmv.v.i v0, 15
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; RV64-NEXT: vslide1down.vx v9, v9, a0
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; RV64-NEXT: vslidedown.vi v9, v8, 4, v0.t
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; RV64-NEXT: vand.vi v8, v9, 1
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; RV64-NEXT: vmsne.vi v0, v8, 0
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; RV64-NEXT: ret
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%2 = shufflevector <16 x i1> %0, <16 x i1> poison, <8 x i32> <i32 5, i32 12, i32 7, i32 2, i32 15, i32 13, i32 4, i32 3>
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ret <8 x i1> %2
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}
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define <4 x i32> @v4i32_v8i32(<8 x i32>) {
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; CHECK-LABEL: v4i32_v8i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: vsrl.vi v10, v10, 1
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; CHECK-NEXT: vrsub.vi v11, v10, 3
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; CHECK-NEXT: vrgather.vv v10, v8, v11
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; CHECK-NEXT: vmv.v.i v0, 5
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; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
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; CHECK-NEXT: vslidedown.vi v8, v8, 4
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
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; CHECK-NEXT: vslidedown.vi v10, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%2 = shufflevector <8 x i32> %0, <8 x i32> poison, <4 x i32> <i32 5, i32 3, i32 7, i32 2>
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ret <4 x i32> %2
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}
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define <4 x i32> @v4i32_v16i32(<16 x i32>) {
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; RV32-LABEL: v4i32_v16i32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; RV32-NEXT: vmv.v.i v12, 1
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; RV32-NEXT: vmv.v.i v14, 6
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; RV32-NEXT: vsetivli zero, 2, e16, m1, tu, ma
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; RV32-NEXT: vslideup.vi v14, v12, 1
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; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; RV32-NEXT: vid.v v12
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; RV32-NEXT: vadd.vv v12, v12, v12
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; RV32-NEXT: vadd.vi v15, v12, 1
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; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; RV32-NEXT: vrgatherei16.vv v12, v8, v15
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; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
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; RV32-NEXT: vmv.v.i v0, 10
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; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
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; RV32-NEXT: vslidedown.vi v8, v8, 8
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; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
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; RV32-NEXT: vrgatherei16.vv v12, v8, v14, v0.t
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; RV32-NEXT: vmv1r.v v8, v12
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4i32_v16i32:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; RV64-NEXT: vid.v v12
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; RV64-NEXT: vadd.vv v12, v12, v12
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; RV64-NEXT: vadd.vi v14, v12, 1
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; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; RV64-NEXT: vrgatherei16.vv v12, v8, v14
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; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
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; RV64-NEXT: vmv.v.i v0, 10
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; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
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; RV64-NEXT: vslidedown.vi v8, v8, 8
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; RV64-NEXT: li a0, 3
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; RV64-NEXT: slli a0, a0, 33
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; RV64-NEXT: addi a0, a0, 1
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; RV64-NEXT: slli a0, a0, 16
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; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; RV64-NEXT: vmv.v.x v10, a0
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; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, mu
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; RV64-NEXT: vrgatherei16.vv v12, v8, v10, v0.t
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; RV64-NEXT: vmv1r.v v8, v12
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; RV64-NEXT: ret
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%2 = shufflevector <16 x i32> %0, <16 x i32> poison, <4 x i32> <i32 1, i32 9, i32 5, i32 14>
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ret <4 x i32> %2
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}
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define <4 x i32> @v4i32_v32i32(<32 x i32>) {
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; RV32-LABEL: v4i32_v32i32:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -256
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; RV32-NEXT: .cfi_def_cfa_offset 256
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; RV32-NEXT: sw ra, 252(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: addi s0, sp, 256
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; RV32-NEXT: .cfi_def_cfa s0, 0
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; RV32-NEXT: andi sp, sp, -128
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; RV32-NEXT: li a0, 32
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; RV32-NEXT: mv a1, sp
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; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
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; RV32-NEXT: vse32.v v8, (a1)
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; RV32-NEXT: lw a0, 36(sp)
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v10, v8, 1
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; RV32-NEXT: vmv.x.s a1, v10
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; RV32-NEXT: vmv.v.x v10, a1
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: lw a0, 120(sp)
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; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; RV32-NEXT: vslidedown.vi v8, v8, 4
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; RV32-NEXT: vmv.x.s a1, v8
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV32-NEXT: vslide1down.vx v8, v10, a1
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; RV32-NEXT: vslide1down.vx v8, v8, a0
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; RV32-NEXT: addi sp, s0, -256
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; RV32-NEXT: lw ra, 252(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s0, 248(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 256
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v4i32_v32i32:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -256
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; RV64-NEXT: .cfi_def_cfa_offset 256
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; RV64-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: addi s0, sp, 256
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; RV64-NEXT: .cfi_def_cfa s0, 0
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; RV64-NEXT: andi sp, sp, -128
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; RV64-NEXT: li a0, 32
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; RV64-NEXT: mv a1, sp
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; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma
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; RV64-NEXT: vse32.v v8, (a1)
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; RV64-NEXT: lw a0, 36(sp)
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; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v10, v8, 1
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; RV64-NEXT: vmv.x.s a1, v10
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; RV64-NEXT: vmv.v.x v10, a1
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: lw a0, 120(sp)
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; RV64-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; RV64-NEXT: vslidedown.vi v8, v8, 4
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; RV64-NEXT: vmv.x.s a1, v8
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; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; RV64-NEXT: vslide1down.vx v8, v10, a1
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; RV64-NEXT: vslide1down.vx v8, v8, a0
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; RV64-NEXT: addi sp, s0, -256
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; RV64-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 256
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; RV64-NEXT: ret
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%2 = shufflevector <32 x i32> %0, <32 x i32> poison, <4 x i32> <i32 1, i32 9, i32 4, i32 30>
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ret <4 x i32> %2
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}
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define <16 x i1> @v16i1_v8i1(<8 x i1>) {
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; CHECK-LABEL: v16i1_v8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
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; CHECK-NEXT: addi a0, a0, %lo(.LCPI4_0)
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vrgather.vv v10, v9, v8
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: ret
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%2 = shufflevector <8 x i1> %0, <8 x i1> poison, <16 x i32> <i32 2, i32 3, i32 0, i32 5, i32 1, i32 2, i32 0, i32 6, i32 2, i32 3, i32 0, i32 7, i32 1, i32 2, i32 0, i32 4>
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ret <16 x i1> %2
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}
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define <8 x i32> @v8i32_v4i32(<4 x i32>) {
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; CHECK-LABEL: v8i32_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
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; CHECK-NEXT: addi a0, a0, %lo(.LCPI5_0)
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vle16.v v12, (a0)
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%2 = shufflevector <4 x i32> %0, <4 x i32> poison, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 1, i32 2, i32 0, i32 3>
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ret <8 x i32> %2
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}
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define <16 x i32> @v16i32_v4i32(<4 x i32>) {
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; CHECK-LABEL: v16i32_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 2
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; CHECK-NEXT: addi a1, a0, 265
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v0, a1
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 3
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; CHECK-NEXT: vmerge.vim v10, v9, 2, v0
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; CHECK-NEXT: lui a1, 4
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; CHECK-NEXT: addi a1, a1, 548
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vmv.s.x v0, a1
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; CHECK-NEXT: addi a0, a0, -1856
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; CHECK-NEXT: vmv.s.x v9, a0
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmerge.vim v10, v10, 0, v0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vsext.vf2 v16, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
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; CHECK-NEXT: vmv.v.v v8, v12
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; CHECK-NEXT: ret
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%2 = shufflevector <4 x i32> %0, <4 x i32> poison, <16 x i32> <i32 2, i32 3, i32 0, i32 2, i32 3, i32 0, i32 1, i32 1, i32 2, i32 0, i32 3, i32 1, i32 1, i32 2, i32 0, i32 3>
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ret <16 x i32> %2
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}
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define <32 x i32> @v32i32_v4i32(<4 x i32>) {
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; CHECK-LABEL: v32i32_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 32
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; CHECK-NEXT: lui a1, 135432
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; CHECK-NEXT: addi a1, a1, 1161
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v0, a1
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; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 3
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; CHECK-NEXT: vmerge.vim v10, v10, 2, v0
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; CHECK-NEXT: lui a0, 270865
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; CHECK-NEXT: addi a0, a0, 548
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; CHECK-NEXT: vmv.s.x v0, a0
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; CHECK-NEXT: lui a0, 100550
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; CHECK-NEXT: addi a0, a0, 64
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; CHECK-NEXT: vmv.s.x v9, a0
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmerge.vim v10, v10, 0, v0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vsext.vf2 v24, v10
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; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v16, v8, v24
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; CHECK-NEXT: vmv.v.v v8, v16
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; CHECK-NEXT: ret
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%2 = shufflevector <4 x i32> %0, <4 x i32> poison, <32 x i32> <i32 2, i32 3, i32 0, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 2, i32 3, i32 0, i32 1, i32 1, i32 2, i32 0, i32 3, i32 1, i32 1, i32 2, i32 0, i32 3, i32 1, i32 2, i32 0, i32 3, i32 1, i32 1, i32 2, i32 0, i32 3>
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ret <32 x i32> %2
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}

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