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davemgreendavemgreen
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[AArch64] Use mov as opposed to And 0xffffffff (#98655)
This adds a tablegen pattern to use ORRWrr (mov) as opposed to i64 AND 0xffffffff, as the mov will implicitly clear the upper bits. This can be seen as a zext(trunc(..)), and could be simpler if it is eliminated.
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10 files changed

+61
-25
lines changed

10 files changed

+61
-25
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2700,6 +2700,11 @@ def : InstAlias<"tst $src1, $src2$sh",
27002700
def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
27012701
def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
27022702

2703+
// Emit (and 0xFFFFFFFF) as a ORRWrr move which may be eliminated.
2704+
let AddedComplexity = 6 in
2705+
def : Pat<(i64 (and GPR64:$Rn, 0xffffffff)),
2706+
(SUBREG_TO_REG (i64 0), (ORRWrr WZR, (EXTRACT_SUBREG GPR64:$Rn, sub_32)), sub_32)>;
2707+
27032708

27042709
//===----------------------------------------------------------------------===//
27052710
// One operand data processing instructions.

‎llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -997,7 +997,7 @@ define i64 @umull_ldr2_d(ptr %x0, i64 %x1) {
997997
; CHECK-LABEL: umull_ldr2_d:
998998
; CHECK: // %bb.0: // %entry
999999
; CHECK-NEXT: ldr w8, [x0]
1000-
; CHECK-NEXT: and x9, x1, #0xffffffff
1000+
; CHECK-NEXT: mov w9, w1
10011001
; CHECK-NEXT: umull x0, w8, w9
10021002
; CHECK-NEXT: ret
10031003
entry:
@@ -1110,7 +1110,7 @@ define i64 @umaddl_ldr2_d(ptr %x0, i64 %x1, i64 %x2) {
11101110
; CHECK-LABEL: umaddl_ldr2_d:
11111111
; CHECK: // %bb.0: // %entry
11121112
; CHECK-NEXT: ldr w8, [x0]
1113-
; CHECK-NEXT: and x9, x1, #0xffffffff
1113+
; CHECK-NEXT: mov w9, w1
11141114
; CHECK-NEXT: umaddl x0, w8, w9, x2
11151115
; CHECK-NEXT: ret
11161116
entry:
@@ -1224,7 +1224,7 @@ define i64 @umnegl_ldr2_d(ptr %x0, i64 %x1) {
12241224
; CHECK-LABEL: umnegl_ldr2_d:
12251225
; CHECK: // %bb.0: // %entry
12261226
; CHECK-NEXT: ldr w8, [x0]
1227-
; CHECK-NEXT: and x9, x1, #0xffffffff
1227+
; CHECK-NEXT: mov w9, w1
12281228
; CHECK-NEXT: umnegl x0, w8, w9
12291229
; CHECK-NEXT: ret
12301230
entry:
@@ -1338,7 +1338,7 @@ define i64 @umsubl_ldr2_d(ptr %x0, i64 %x1, i64 %x2) {
13381338
; CHECK-LABEL: umsubl_ldr2_d:
13391339
; CHECK: // %bb.0: // %entry
13401340
; CHECK-NEXT: ldr w8, [x0]
1341-
; CHECK-NEXT: and x9, x1, #0xffffffff
1341+
; CHECK-NEXT: mov w9, w1
13421342
; CHECK-NEXT: umsubl x0, w8, w9, x2
13431343
; CHECK-NEXT: ret
13441344
entry:
@@ -1400,7 +1400,7 @@ define i64 @umull_and_lshr(i64 %x) {
14001400
; CHECK-LABEL: umull_and_lshr:
14011401
; CHECK: // %bb.0:
14021402
; CHECK-NEXT: lsr x8, x0, #32
1403-
; CHECK-NEXT: and x9, x0, #0xffffffff
1403+
; CHECK-NEXT: mov w9, w0
14041404
; CHECK-NEXT: umull x0, w9, w8
14051405
; CHECK-NEXT: ret
14061406
%lo = and i64 %x, u0xffffffff
@@ -1424,7 +1424,7 @@ define i64 @umaddl_and_lshr(i64 %x, i64 %a) {
14241424
; CHECK-LABEL: umaddl_and_lshr:
14251425
; CHECK: // %bb.0:
14261426
; CHECK-NEXT: lsr x8, x0, #32
1427-
; CHECK-NEXT: and x9, x0, #0xffffffff
1427+
; CHECK-NEXT: mov w9, w0
14281428
; CHECK-NEXT: umaddl x0, w9, w8, x1
14291429
; CHECK-NEXT: ret
14301430
%lo = and i64 %x, u0xffffffff
@@ -1437,8 +1437,8 @@ define i64 @umaddl_and_lshr(i64 %x, i64 %a) {
14371437
define i64 @umaddl_and_and(i64 %x, i64 %y, i64 %a) {
14381438
; CHECK-LABEL: umaddl_and_and:
14391439
; CHECK: // %bb.0:
1440-
; CHECK-NEXT: and x8, x0, #0xffffffff
1441-
; CHECK-NEXT: and x9, x1, #0xffffffff
1440+
; CHECK-NEXT: mov w8, w0
1441+
; CHECK-NEXT: mov w9, w1
14421442
; CHECK-NEXT: umaddl x0, w8, w9, x2
14431443
; CHECK-NEXT: ret
14441444
%lo = and i64 %x, u0xffffffff

‎llvm/test/CodeGen/AArch64/and-mask-removal.ll

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -549,3 +549,33 @@ define i64 @test_2_selects(i8 zeroext %a) {
549549
}
550550

551551
declare i8 @llvm.usub.sat.i8(i8, i8) #0
552+
553+
define i64 @and0xffffffff(i64 %a) nounwind ssp {
554+
; CHECK-LABEL: and0xffffffff:
555+
; CHECK: ; %bb.0: ; %entry
556+
; CHECK-NEXT: mov w0, w0
557+
; CHECK-NEXT: ret
558+
entry:
559+
%b = and i64 %a, u0xffffffff
560+
ret i64 %b
561+
}
562+
563+
define i64 @and0xfffffff0(i64 %a) nounwind ssp {
564+
; CHECK-LABEL: and0xfffffff0:
565+
; CHECK: ; %bb.0: ; %entry
566+
; CHECK-NEXT: and x0, x0, #0xfffffff0
567+
; CHECK-NEXT: ret
568+
entry:
569+
%b = and i64 %a, u0xfffffff0
570+
ret i64 %b
571+
}
572+
573+
define i64 @and0x7fffffff(i64 %a) nounwind ssp {
574+
; CHECK-LABEL: and0x7fffffff:
575+
; CHECK: ; %bb.0: ; %entry
576+
; CHECK-NEXT: and x0, x0, #0x7fffffff
577+
; CHECK-NEXT: ret
578+
entry:
579+
%b = and i64 %a, u0x7fffffff
580+
ret i64 %b
581+
}

‎llvm/test/CodeGen/AArch64/arm64-2012-05-09-LOADgot-bug.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ entry:
88
store i64 %ext, ptr %addr, align 8
99
; CHECK: adrp x{{[0-9]+}}, _x@GOTPAGE
1010
; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}, _x@GOTPAGEOFF]
11-
; CHECK-NEXT: and x{{[0-9]+}}, x{{[0-9]+}}, #0xffffffff
11+
; CHECK-NEXT: mov w{{[0-9]+}}, w{{[0-9]+}}
1212
; CHECK-NEXT: str x{{[0-9]+}}, [x{{[0-9]+}}]
1313
ret void
1414
}

‎llvm/test/CodeGen/AArch64/arm64_32-memcpy.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,9 @@
22

33
define i64 @test_memcpy(ptr %addr, ptr %src, i1 %tst) minsize {
44
; CHECK-LABEL: test_memcpy:
5-
; CHECK: ldr [[VAL64:x[0-9]+]], [x0]
5+
; CHECK: ldr x[[VAL64:[0-9]+]], [x0]
66
; [...]
7-
; CHECK: and x0, [[VAL64]], #0xffffffff
7+
; CHECK: mov w0, w[[VAL64]]
88
; CHECK: bl _memcpy
99

1010
%val64 = load i64, ptr %addr
@@ -22,9 +22,9 @@ false:
2222

2323
define i64 @test_memmove(ptr %addr, ptr %src, i1 %tst) minsize {
2424
; CHECK-LABEL: test_memmove:
25-
; CHECK: ldr [[VAL64:x[0-9]+]], [x0]
25+
; CHECK: ldr x[[VAL64:[0-9]+]], [x0]
2626
; [...]
27-
; CHECK: and x0, [[VAL64]], #0xffffffff
27+
; CHECK: mov w0, w[[VAL64]]
2828
; CHECK: bl _memmove
2929

3030
%val64 = load i64, ptr %addr
@@ -42,9 +42,9 @@ false:
4242

4343
define i64 @test_memset(ptr %addr, ptr %src, i1 %tst) minsize {
4444
; CHECK-LABEL: test_memset:
45-
; CHECK: ldr [[VAL64:x[0-9]+]], [x0]
45+
; CHECK: ldr x[[VAL64:[0-9]+]], [x0]
4646
; [...]
47-
; CHECK: and x0, [[VAL64]], #0xffffffff
47+
; CHECK: mov w0, w[[VAL64]]
4848
; CHECK: bl _memset
4949

5050
%val64 = load i64, ptr %addr

‎llvm/test/CodeGen/AArch64/arm64_32-pointer-extend.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

33
define void @pass_pointer(i64 %in) {
44
; CHECK-LABEL: pass_pointer:
5-
; CHECK: and x0, x0, #0xffffffff
5+
; CHECK: mov w0, w0
66
; CHECK: bl _take_pointer
77

88
%in32 = trunc i64 %in to i32
@@ -39,8 +39,8 @@ define void @caller_ptr_stack_slot(ptr %ptr) {
3939

4040
define ptr @return_ptr(i64 %in, i64 %r) {
4141
; CHECK-LABEL: return_ptr:
42-
; CHECK: sdiv [[VAL64:x[0-9]+]], x0, x1
43-
; CHECK: and x0, [[VAL64]], #0xffffffff
42+
; CHECK: sdiv x[[VAL64:[0-9]+]], x0, x1
43+
; CHECK: mov w0, w[[VAL64]]
4444

4545
%sum = sdiv i64 %in, %r
4646
%sum32 = trunc i64 %sum to i32

‎llvm/test/CodeGen/AArch64/arm64_32.ll

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -598,7 +598,7 @@ define void @test_asm_memory(ptr %base.addr) {
598598

599599
define void @test_unsafe_asm_memory(i64 %val) {
600600
; CHECK-LABEL: test_unsafe_asm_memory:
601-
; CHECK: and x[[ADDR:[0-9]+]], x0, #0xffffffff
601+
; CHECK: mov w[[ADDR:[0-9]+]], w0
602602
; CHECK: str wzr, [x[[ADDR]]]
603603
%addr_int = trunc i64 %val to i32
604604
%addr = inttoptr i32 %addr_int to ptr
@@ -615,7 +615,8 @@ define [9 x ptr] @test_demoted_return(ptr %in) {
615615

616616
define ptr @test_inttoptr(i64 %in) {
617617
; CHECK-LABEL: test_inttoptr:
618-
; CHECK: and x0, x0, #0xffffffff
618+
; CHECK-OPT: mov w0, w0
619+
; CHECK-FAST: and x0, x0, #0xffffffff
619620
%res = inttoptr i64 %in to ptr
620621
ret ptr %res
621622
}
@@ -732,7 +733,7 @@ define ptr @test_gep_nonpow2(ptr %a0, i32 %a1) {
732733
define void @test_memset(i64 %in, i8 %value) {
733734
; CHECK-LABEL: test_memset:
734735
; CHECK-DAG: lsr x2, x0, #32
735-
; CHECK-DAG: and x0, x0, #0xffffffff
736+
; CHECK-DAG: mov w0, w0
736737
; CHECK: b _memset
737738

738739
%ptr.i32 = trunc i64 %in to i32
@@ -746,7 +747,7 @@ define void @test_memset(i64 %in, i8 %value) {
746747
define void @test_bzero(i64 %in) {
747748
; CHECK-LABEL: test_bzero:
748749
; CHECK-DAG: lsr x1, x0, #32
749-
; CHECK-DAG: and x0, x0, #0xffffffff
750+
; CHECK-DAG: mov w0, w0
750751
; CHECK: b _bzero
751752

752753
%ptr.i32 = trunc i64 %in to i32

‎llvm/test/CodeGen/AArch64/bitfield.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ define dso_local void @test_zext_inreg_64(i64 %in) {
173173
%trunc_i32 = trunc i64 %in to i32
174174
%zext_i32 = zext i32 %trunc_i32 to i64
175175
store volatile i64 %zext_i32, ptr @var64
176-
; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, #0xffffffff
176+
; CHECK: mov {{w[0-9]+}}, {{w[0-9]+}}
177177

178178
ret void
179179
}

‎llvm/test/CodeGen/AArch64/pr58431.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ define i32 @f(i64 %0) {
55
; CHECK-LABEL: f:
66
; CHECK: // %bb.0:
77
; CHECK-NEXT: mov w8, #10 // =0xa
8-
; CHECK-NEXT: and x9, x0, #0xffffffff
8+
; CHECK-NEXT: mov w9, w0
99
; CHECK-NEXT: udiv x10, x9, x8
1010
; CHECK-NEXT: msub x0, x10, x8, x9
1111
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0

‎llvm/test/CodeGen/AArch64/swifterror.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -977,7 +977,7 @@ define float @foo_vararg(ptr swifterror %error_ptr_ref, ...) {
977977
; CHECK-APPLE-ARM64_32-NEXT: add x9, x29, #16
978978
; CHECK-APPLE-ARM64_32-NEXT: strb w8, [x0, #8]
979979
; CHECK-APPLE-ARM64_32-NEXT: orr w8, w9, #0x4
980-
; CHECK-APPLE-ARM64_32-NEXT: and x10, x9, #0xfffffff0
980+
; CHECK-APPLE-ARM64_32-NEXT: mov w10, w9
981981
; CHECK-APPLE-ARM64_32-NEXT: stur w8, [x29, #-8]
982982
; CHECK-APPLE-ARM64_32-NEXT: ldr w11, [x10]
983983
; CHECK-APPLE-ARM64_32-NEXT: orr w10, w9, #0x8

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