AMDGPU/GlobalISel: Add skeletons for new register bank select passes

New register bank select for AMDGPU will be split in two passes:
RBSelect: select banks based on machine uniformity analysis
RBLegalize: lower instructions that can't be inst-selected with register
banks assigned by RBSelect. Does not change already assigned banks.
Similar to legalizer but with context of uniformity analysis.
RBLegalize main goal is to provide high level table-like overview of how
to lower generic instructions based on available target features and
uniformity info (uniform vs divergent). See RegBankLegalizeRules.

Summary of new features:
At the moment reg bank select assigns register bank to output register
using simple algorithm:
- one of the inputs is vgpr output is vgpr
- all inputs are sgpr output is sgpr.
When function does not contain divergent control flow propagating reg
banks like this works. In general, first point is still correct but
second is not when function contains divergent control flow. Examples:
- Phi with uniform inputs that go through divergent branch
- Instruction with temporal divergent use.
To fix this RB-select will use machine uniformity analysis to assign
vgpr to each divergent and sgpr to each uniform instruction.
But some instructions are only available on VALU (for example floating
point instructions before gfx1150) and we need to assign vgpr to them.
Since we are no longer propagating reg banks we need to ensure that
uniform instructions get their inputs in sgpr in some way.
In RB-legalize uniform instructions that are only available on VALU will
be reassigned to vgpr on all operands and readfirstlane vgpr output to
original sgpr output.

Author: petar-avramovic

llvm/lib/Target/AMDGPU/AMDGPU.h

@@ -39,6 +39,8 @@ FunctionPass *createSIFoldOperandsLegacyPass();
 FunctionPass *createSIPeepholeSDWALegacyPass();
 FunctionPass *createSILowerI1CopiesLegacyPass();
 FunctionPass *createAMDGPUGlobalISelDivergenceLoweringPass();
+FunctionPass *createAMDGPURBSelectPass();
+FunctionPass *createAMDGPURBLegalizePass();
 FunctionPass *createSIShrinkInstructionsLegacyPass();
 FunctionPass *createSILoadStoreOptimizerLegacyPass();
 FunctionPass *createSIWholeQuadModePass();
@@ -188,6 +190,12 @@ extern char &SILowerI1CopiesLegacyID;
 void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &);
 extern char &AMDGPUGlobalISelDivergenceLoweringID;
 
+void initializeAMDGPURBSelectPass(PassRegistry &);
+extern char &AMDGPURBSelectID;
+
+void initializeAMDGPURBLegalizePass(PassRegistry &);
+extern char &AMDGPURBLegalizeID;
+
 void initializeAMDGPUMarkLastScratchLoadPass(PassRegistry &);
 extern char &AMDGPUMarkLastScratchLoadID;
 

llvm/lib/Target/AMDGPU/AMDGPURBLegalize.cpp

@@ -0,0 +1,74 @@
+//===-- AMDGPURBLegalize.cpp ----------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// Lower G_ instructions that can't be inst-selected with register bank
+/// assignment given by RB-select based on machine uniformity info.
+/// Given types on all operands, some register bank assignments require lowering
+/// while other do not.
+/// Note: cases where all register bank assignments would require lowering are
+/// lowered in legalizer.
+/// For example vgpr S64 G_AND requires lowering to S32 while SGPR S64 does not.
+/// Eliminate sgpr S1 by lowering to sgpr S32.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPU.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/InitializePasses.h"
+
+#define DEBUG_TYPE "rb-legalize"
+
+using namespace llvm;
+
+namespace {
+
+class AMDGPURBLegalize : public MachineFunctionPass {
+public:
+  static char ID;
+
+public:
+  AMDGPURBLegalize() : MachineFunctionPass(ID) {
+    initializeAMDGPURBLegalizePass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override { return "AMDGPU RB Legalize"; }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  // If there were no phis and we do waterfall expansion machine verifier would
+  // fail.
+  MachineFunctionProperties getClearedProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::NoPHIs);
+  }
+};
+
+} // End anonymous namespace.
+
+INITIALIZE_PASS_BEGIN(AMDGPURBLegalize, DEBUG_TYPE, "AMDGPU RB Legalize", false,
+                      false)
+INITIALIZE_PASS_END(AMDGPURBLegalize, DEBUG_TYPE, "AMDGPU RB Legalize", false,
+                    false)
+
+char AMDGPURBLegalize::ID = 0;
+
+char &llvm::AMDGPURBLegalizeID = AMDGPURBLegalize::ID;
+
+FunctionPass *llvm::createAMDGPURBLegalizePass() {
+  return new AMDGPURBLegalize();
+}
+
+using namespace AMDGPU;
+
+bool AMDGPURBLegalize::runOnMachineFunction(MachineFunction &MF) {
+  return true;
+}

llvm/lib/Target/AMDGPU/AMDGPURBSelect.cpp

@@ -0,0 +1,66 @@
+//===-- AMDGPURBSelect.cpp ------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// Assign register banks to all register operands of G_ instructions using
+/// machine uniformity analysis.
+/// SGPR - uniform values and some lane masks
+/// VGPR - divergent, non S1, values
+/// VCC  - divergent S1 values(lane masks)
+/// However in some cases G_ instructions with this register bank assignment
+/// can't be inst-selected. This is solved in RBLegalize.
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPU.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/InitializePasses.h"
+
+#define DEBUG_TYPE "rb-select"
+
+using namespace llvm;
+
+namespace {
+
+class AMDGPURBSelect : public MachineFunctionPass {
+public:
+  static char ID;
+
+public:
+  AMDGPURBSelect() : MachineFunctionPass(ID) {
+    initializeAMDGPURBSelectPass(*PassRegistry::getPassRegistry());
+  }
+
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override { return "AMDGPU RB select"; }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    MachineFunctionPass::getAnalysisUsage(AU);
+  }
+
+  // This pass assigns register banks to all virtual registers, and we maintain
+  // this property in subsequent passes
+  MachineFunctionProperties getSetProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::RegBankSelected);
+  }
+};
+
+} // End anonymous namespace.
+
+INITIALIZE_PASS_BEGIN(AMDGPURBSelect, DEBUG_TYPE, "AMDGPU RB select", false,
+                      false)
+INITIALIZE_PASS_END(AMDGPURBSelect, DEBUG_TYPE, "AMDGPU RB select", false,
+                    false)
+
+char AMDGPURBSelect::ID = 0;
+
+char &llvm::AMDGPURBSelectID = AMDGPURBSelect::ID;
+
+FunctionPass *llvm::createAMDGPURBSelectPass() { return new AMDGPURBSelect(); }
+
+bool AMDGPURBSelect::runOnMachineFunction(MachineFunction &MF) { return true; }

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -443,6 +443,11 @@ static cl::opt<bool>
                            cl::desc("Enable AMDGPUAttributorPass"),
                            cl::init(true), cl::Hidden);
 
+static cl::opt<bool> NewRegBankSelect(
+    "new-reg-bank-select",
+    cl::desc("Run rb-select and rb-legalize instead of amdgpu-regbankselect"),
+    cl::init(false), cl::Hidden);
+
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   // Register the target
   RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
@@ -459,6 +464,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeGCNDPPCombineLegacyPass(*PR);
   initializeSILowerI1CopiesLegacyPass(*PR);
   initializeAMDGPUGlobalISelDivergenceLoweringPass(*PR);
+  initializeAMDGPURBSelectPass(*PR);
+  initializeAMDGPURBLegalizePass(*PR);
   initializeSILowerWWMCopiesPass(*PR);
   initializeAMDGPUMarkLastScratchLoadPass(*PR);
   initializeSILowerSGPRSpillsLegacyPass(*PR);
@@ -1371,7 +1378,12 @@ void GCNPassConfig::addPreRegBankSelect() {
 }
 
 bool GCNPassConfig::addRegBankSelect() {
-  addPass(new AMDGPURegBankSelect());
+  if (NewRegBankSelect) {
+    addPass(createAMDGPURBSelectPass());
+    addPass(createAMDGPURBLegalizePass());
+  } else {
+    addPass(new AMDGPURegBankSelect());
+  }
   return false;
 }
 

llvm/lib/Target/AMDGPU/CMakeLists.txt

@@ -57,6 +57,8 @@ add_llvm_target(AMDGPUCodeGen
   AMDGPUExportClustering.cpp
   AMDGPUFrameLowering.cpp
   AMDGPUGlobalISelDivergenceLowering.cpp
+  AMDGPURBSelect.cpp
+  AMDGPURBLegalize.cpp
   AMDGPUGlobalISelUtils.cpp
   AMDGPUHSAMetadataStreamer.cpp
   AMDGPUInsertDelayAlu.cpp