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lukel97lukel97
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Swap operand order to match generic case
1 parent 55bbe70 commit ff42a4f

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5 files changed

+297
-305
lines changed

5 files changed

+297
-305
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5239,12 +5239,12 @@ static SDValue lowerDisjointIndicesShuffle(ShuffleVectorSDNode *SVN,
52395239
if (Lane == -1)
52405240
SelectMaskVals.push_back(DAG.getUNDEF(XLenVT));
52415241
else
5242-
SelectMaskVals.push_back(DAG.getConstant(Lane, DL, XLenVT));
5242+
SelectMaskVals.push_back(DAG.getConstant(Lane ? 0 : 1, DL, XLenVT));
52435243
}
52445244
MVT MaskVT = VT.changeVectorElementType(MVT::i1);
52455245
SDValue SelectMask = DAG.getBuildVector(MaskVT, DL, SelectMaskVals);
52465246
SDValue Select = DAG.getNode(ISD::VSELECT, DL, VT, SelectMask,
5247-
SVN->getOperand(1), SVN->getOperand(0));
5247+
SVN->getOperand(0), SVN->getOperand(1));
52485248

52495249
// Move all indices relative to the first source.
52505250
SmallVector<int> NewMask(Mask.size());

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -29,10 +29,10 @@ define <4 x half> @shuffle_v4f16(<4 x half> %x, <4 x half> %y) {
2929
define <8 x float> @shuffle_v8f32(<8 x float> %x, <8 x float> %y) {
3030
; CHECK-LABEL: shuffle_v8f32:
3131
; CHECK: # %bb.0:
32-
; CHECK-NEXT: li a0, 19
32+
; CHECK-NEXT: li a0, -20
3333
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
3434
; CHECK-NEXT: vmv.s.x v0, a0
35-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
35+
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
3636
; CHECK-NEXT: ret
3737
%s = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 8, i32 9, i32 2, i32 3, i32 12, i32 5, i32 6, i32 7>
3838
ret <8 x float> %s
@@ -403,10 +403,10 @@ define <16 x float> @shuffle_disjoint_lanes(<16 x float> %v, <16 x float> %w) {
403403
; CHECK-NEXT: addi a0, a0, %lo(.LCPI30_0)
404404
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
405405
; CHECK-NEXT: vle8.v v16, (a0)
406-
; CHECK-NEXT: lui a0, 5
407-
; CHECK-NEXT: addi a0, a0, 1365
406+
; CHECK-NEXT: lui a0, 11
407+
; CHECK-NEXT: addi a0, a0, -1366
408408
; CHECK-NEXT: vmv.s.x v0, a0
409-
; CHECK-NEXT: vmerge.vvm v12, v8, v12, v0
409+
; CHECK-NEXT: vmerge.vvm v12, v12, v8, v0
410410
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
411411
; CHECK-NEXT: vsext.vf2 v18, v16
412412
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
@@ -423,9 +423,9 @@ define <16 x float> @shuffle_disjoint_lanes_one_identity(<16 x float> %v, <16 x
423423
; CHECK-NEXT: addi a0, a0, %lo(.LCPI31_0)
424424
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
425425
; CHECK-NEXT: vle8.v v16, (a0)
426-
; CHECK-NEXT: li a0, -304
426+
; CHECK-NEXT: li a0, 271
427427
; CHECK-NEXT: vmv.s.x v0, a0
428-
; CHECK-NEXT: vmerge.vvm v12, v8, v12, v0
428+
; CHECK-NEXT: vmerge.vvm v12, v12, v8, v0
429429
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
430430
; CHECK-NEXT: vsext.vf2 v18, v16
431431
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,10 @@ define <4 x i16> @shuffle_v4i16(<4 x i16> %x, <4 x i16> %y) {
1616
define <8 x i32> @shuffle_v8i32(<8 x i32> %x, <8 x i32> %y) {
1717
; CHECK-LABEL: shuffle_v8i32:
1818
; CHECK: # %bb.0:
19-
; CHECK-NEXT: li a0, 52
19+
; CHECK-NEXT: li a0, 203
2020
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
2121
; CHECK-NEXT: vmv.s.x v0, a0
22-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
22+
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
2323
; CHECK-NEXT: ret
2424
%s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 1, i32 10, i32 3, i32 12, i32 13, i32 6, i32 7>
2525
ret <8 x i32> %s
@@ -455,9 +455,9 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) {
455455
; CHECK-NEXT: addi a0, a0, %lo(.LCPI26_0)
456456
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
457457
; CHECK-NEXT: vle8.v v10, (a0)
458-
; CHECK-NEXT: li a0, 65
458+
; CHECK-NEXT: li a0, 20
459459
; CHECK-NEXT: vmv.s.x v0, a0
460-
; CHECK-NEXT: vmerge.vvm v9, v8, v9, v0
460+
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
461461
; CHECK-NEXT: vrgather.vv v8, v9, v10
462462
; CHECK-NEXT: ret
463463
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2>
@@ -688,9 +688,9 @@ define <8 x i8> @unmergable(<8 x i8> %v, <8 x i8> %w) {
688688
; CHECK-NEXT: addi a0, a0, %lo(.LCPI46_0)
689689
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
690690
; CHECK-NEXT: vle8.v v10, (a0)
691-
; CHECK-NEXT: li a0, 171
691+
; CHECK-NEXT: li a0, 84
692692
; CHECK-NEXT: vmv.s.x v0, a0
693-
; CHECK-NEXT: vmerge.vvm v9, v8, v9, v0
693+
; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
694694
; CHECK-NEXT: vrgather.vv v8, v9, v10
695695
; CHECK-NEXT: ret
696696
%res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 9, i32 4, i32 11, i32 6, i32 13, i32 8, i32 15>
@@ -702,9 +702,9 @@ define <8 x i32> @shuffle_v8i32_2(<8 x i32> %x, <8 x i32> %y) {
702702
; CHECK-LABEL: shuffle_v8i32_2:
703703
; CHECK: # %bb.0:
704704
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
705-
; CHECK-NEXT: vmv.v.i v0, 12
705+
; CHECK-NEXT: vmv.v.i v0, -13
706706
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
707-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
707+
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
708708
; CHECK-NEXT: ret
709709
%s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 1, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
710710
ret <8 x i32> %s
@@ -1022,10 +1022,10 @@ define <16 x i32> @shuffle_disjoint_lanes(<16 x i32> %v, <16 x i32> %w) {
10221022
; CHECK-NEXT: addi a0, a0, %lo(.LCPI70_0)
10231023
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
10241024
; CHECK-NEXT: vle8.v v16, (a0)
1025-
; CHECK-NEXT: lui a0, 5
1026-
; CHECK-NEXT: addi a0, a0, 1365
1025+
; CHECK-NEXT: lui a0, 11
1026+
; CHECK-NEXT: addi a0, a0, -1366
10271027
; CHECK-NEXT: vmv.s.x v0, a0
1028-
; CHECK-NEXT: vmerge.vvm v12, v8, v12, v0
1028+
; CHECK-NEXT: vmerge.vvm v12, v12, v8, v0
10291029
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
10301030
; CHECK-NEXT: vsext.vf2 v18, v16
10311031
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
@@ -1042,9 +1042,9 @@ define <16 x i32> @shuffle_disjoint_lanes_one_identity(<16 x i32> %v, <16 x i32>
10421042
; CHECK-NEXT: addi a0, a0, %lo(.LCPI71_0)
10431043
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
10441044
; CHECK-NEXT: vle8.v v16, (a0)
1045-
; CHECK-NEXT: li a0, -304
1045+
; CHECK-NEXT: li a0, 271
10461046
; CHECK-NEXT: vmv.s.x v0, a0
1047-
; CHECK-NEXT: vmerge.vvm v12, v8, v12, v0
1047+
; CHECK-NEXT: vmerge.vvm v12, v12, v8, v0
10481048
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
10491049
; CHECK-NEXT: vsext.vf2 v18, v16
10501050
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma

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